OTP_CTRL Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: `1cb1c3d135`

Branch: os_regression_2024_10_02

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	2.680s	192.263us	1	1	100.00
V1	smoke	otp_ctrl_smoke	34.510s	5.266ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	4.620s	1.461ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	2.110s	120.684us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	9.960s	518.529us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	6.990s	2.580ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	4.920s	437.619us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	2.110s	120.684us	20	20	100.00
		otp_ctrl_csr_aliasing	6.990s	2.580ms	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	1.650s	79.800us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	1.750s	53.120us	5	5	100.00
V1		TOTAL			114	116	98.28
V2	dai_access_partition_walk	otp_ctrl_partition_walk	34.810s	5.086ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	11.960s	1.893ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	1.039m	3.069ms	10	10	100.00
		otp_ctrl_check_fail	1.372m	12.098ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	18.330s	4.647ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	1.092m	21.829ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.869m	4.894ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	45.690s	10.724ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	42.690s	16.046ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	1.524m	22.505ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	4.451m	21.521ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	1.563m	7.950ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	22.742m	171.396ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	2.310s	593.621us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	6.040s	570.617us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	7.270s	731.481us	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	7.270s	731.481us	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	4.620s	1.461ms	5	5	100.00
		otp_ctrl_csr_rw	2.110s	120.684us	20	20	100.00
		otp_ctrl_csr_aliasing	6.990s	2.580ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	6.060s	1.924ms	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	4.620s	1.461ms	5	5	100.00
		otp_ctrl_csr_rw	2.110s	120.684us	20	20	100.00
		otp_ctrl_csr_aliasing	6.990s	2.580ms	5	5	100.00
		otp_ctrl_same_csr_outstanding	6.060s	1.924ms	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
		otp_ctrl_tl_intg_err	27.160s	18.869ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	27.160s	18.869ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	34.510s	5.266ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	34.510s	5.266ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.690s	16.046ms	200	200	100.00
		otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.690s	16.046ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.690s	16.046ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.690s	16.046ms	200	200	100.00
		otp_ctrl_macro_errs	4.451m	21.521ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.690s	16.046ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	42.690s	16.046ms	200	200	100.00
		otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.690s	16.046ms	200	200	100.00
		otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.690s	16.046ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.690s	16.046ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.690s	16.046ms	200	200	100.00
		otp_ctrl_macro_errs	4.451m	21.521ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.690s	16.046ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	42.690s	16.046ms	200	200	100.00
		otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	11.960s	1.893ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	1.372m	12.098ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	1.092m	21.829ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	1.092m	21.829ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	1.092m	21.829ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	1.092m	21.829ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	1.092m	21.829ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	34.510s	5.266ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	1.092m	21.829ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	34.510s	5.266ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	5.360m	154.708ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	18.330s	4.647ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	34.510s	5.266ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	34.510s	5.266ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	4.451m	21.521ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	15.550s	3.023ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	4.205m	15.431ms	41	100	41.00
V3		TOTAL			42	101	41.58
		TOTAL			1282	1343	95.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.91	93.58	96.65	95.54	91.81	97.35	96.23	93.21

Failure Buckets

UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 30 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 30 failures.
  - 0.otp_ctrl_stress_all_with_rand_reset.34971927423490475192221865169092156230811376262689906957744483245879853610285
    Line 10227, in log /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3698957603 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 3 [0x3]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 3698957603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.otp_ctrl_stress_all_with_rand_reset.88524666249939686259758543769665142155285844436599749694734388124866680179768
    Line 102, in log /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 113480136 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
  UVM_INFO @ 113480136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 28 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 13 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 13 failures.
  - 9.otp_ctrl_stress_all_with_rand_reset.83464369407583548515498353050494832776935738372796088421892874184176642426279
    Line 10113, in log /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2644860311 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2388779420 [0x8e61e19c] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 2644860311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.otp_ctrl_stress_all_with_rand_reset.4513123409593854962279965884812603497014607379266671917795478805352489601221
    Line 27496, in log /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 13061257827 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (587995040 [0x230c17a0] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
  UVM_INFO @ 13061257827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
Offending '(cio_test_en_o == *)' has 5 failures:
- Test otp_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 0.otp_ctrl_csr_mem_rw_with_rand_reset.86956057308322867495306845423800444253079248647116271157119811800716814844022
    Line 80, in log /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 429923057 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 429923057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 18.otp_ctrl_csr_mem_rw_with_rand_reset.90472389778118922748807671057866247664885756417709719220248798015424460668316
    Line 80, in log /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @  36473792 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @  36473792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 24.otp_ctrl_stress_all_with_rand_reset.111901501886815694945728162192953411390144431997423193225688884633100237405479
    Line 385, in log /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 7489384793 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 7489384793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 71.otp_ctrl_stress_all_with_rand_reset.21771404559059034727140455258177997716259404765927411414564839486321389601423
    Line 3363, in log /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/71.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
      Offending '(cio_test_en_o == 0)'
  UVM_ERROR @ 684320434 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
  UVM_INFO @ 684320434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:867) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 4 failures.
  - 10.otp_ctrl_stress_all_with_rand_reset.793347652983188850433355460774707570584183320275483651585935201009670314353
    Line 11138, in log /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 30231301119 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 30231301119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.otp_ctrl_stress_all_with_rand_reset.48493217007898874417630413098633952466740754631013411638778451964099877153975
    Line 18715, in log /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 34566157940 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 34566157940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 3 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 3 failures.
  - 19.otp_ctrl_stress_all_with_rand_reset.61906755905517676487074464564895750783390188565092113737784200990927035967432
    Line 59737, in log /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 64911952576 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 64911952576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 52.otp_ctrl_stress_all_with_rand_reset.113308920120689321186818413265143365567363058760833208845351746954479690325999
    Line 11628, in log /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/52.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 514743452 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
  UVM_INFO @ 514743452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *fc rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 2.otp_ctrl_stress_all_with_rand_reset.53467775377288530163520159557252744297488914555949041963529681174125890180104
    Line 19907, in log /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12211586499 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1256637605 [0x4ae6c4a5]) dai addr 6fc rdata0 readout mismatch
  UVM_INFO @ 12211586499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_*' is being accessed has 1 failures:

Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

17.otp_ctrl_stress_all_with_rand_reset.77511991772029283932259213093880360580246101694595733299702690688110943448087
Line 4484, in log /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @ 1170305492 ps: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'err_code' while register 'otp_ctrl_core_reg_block.err_code_12' is being accessed
  UVM_INFO @ 1171328756 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 1171538060 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 1172584580 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1
  UVM_INFO @ 1172770628 ps: (otp_ctrl_scoreboard.sv:569) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] sw state 1, reg state          1

UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 60.otp_ctrl_stress_all_with_rand_reset.24384447370958519094529940825767519594978550821250881841970765604433151769759
    Line 9843, in log /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/60.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14677665506 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 3096339946 [0xb88e65ea]) dai addr 744 rdata0 readout mismatch
  UVM_INFO @ 14677665506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *c rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 69.otp_ctrl_stress_all_with_rand_reset.2092547807191533990135857875775022474383711631572545153940091756015124747124
    Line 189, in log /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/69.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6690265738 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 812 [0x32c]) dai addr 32c rdata0 readout mismatch
  UVM_INFO @ 6690265738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:608) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=466) has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 77.otp_ctrl_stress_all_with_rand_reset.109251345487142524033902334504177882554972048449363066675210699143963576061296
    Line 54891, in log /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/77.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 61351004186 ps: (csr_utils_pkg.sv:608) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=0xc2b35010, Comparison=CompareOpEq, exp_data=0x0, call_count=466)
  UVM_INFO @ 61351004186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *f* rdata* readout mismatch has 1 failures:
- Test otp_ctrl_stress_all_with_rand_reset has 1 failures.
  - 93.otp_ctrl_stress_all_with_rand_reset.40214982052849705902133326426240742498629046832362982144999209374516132173307
    Line 11826, in log /workspaces/repo/scratch/os_regression_2024_10_02/otp_ctrl-sim-vcs/93.otp_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9000413865 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 1272 [0x4f8]) dai addr 4f8 rdata0 readout mismatch
  UVM_INFO @ 9000413865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```