OTP_CTRL Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: 29d22a60a2

Branch: os_regression_2024_10_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	otp_ctrl_wake_up	3.770s	797.918us	1	1	100.00
V1	smoke	otp_ctrl_smoke	18.590s	7.791ms	50	50	100.00
V1	csr_hw_reset	otp_ctrl_csr_hw_reset	4.880s	1.606ms	5	5	100.00
V1	csr_rw	otp_ctrl_csr_rw	4.690s	682.370us	20	20	100.00
V1	csr_bit_bash	otp_ctrl_csr_bit_bash	8.930s	130.883us	5	5	100.00
V1	csr_aliasing	otp_ctrl_csr_aliasing	8.880s	307.190us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otp_ctrl_csr_mem_rw_with_rand_reset	6.100s	107.473us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	otp_ctrl_csr_rw	4.690s	682.370us	20	20	100.00
		otp_ctrl_csr_aliasing	8.880s	307.190us	5	5	100.00
V1	mem_walk	otp_ctrl_mem_walk	2.400s	545.562us	5	5	100.00
V1	mem_partial_access	otp_ctrl_mem_partial_access	2.840s	537.463us	5	5	100.00
V1		TOTAL			115	116	99.14
V2	dai_access_partition_walk	otp_ctrl_partition_walk	33.910s	9.938ms	1	1	100.00
V2	init_fail	otp_ctrl_init_fail	13.430s	2.873ms	300	300	100.00
V2	partition_check	otp_ctrl_background_chks	33.530s	1.521ms	10	10	100.00
		otp_ctrl_check_fail	58.300s	4.225ms	50	50	100.00
V2	regwen_during_otp_init	otp_ctrl_regwen	20.340s	5.258ms	50	50	100.00
V2	partition_lock	otp_ctrl_dai_lock	48.100s	13.759ms	50	50	100.00
V2	interface_key_check	otp_ctrl_parallel_key_req	1.887m	7.585ms	50	50	100.00
V2	lc_interactions	otp_ctrl_parallel_lc_req	36.700s	11.267ms	50	50	100.00
		otp_ctrl_parallel_lc_esc	28.770s	10.590ms	200	200	100.00
V2	otp_dai_errors	otp_ctrl_dai_errs	49.100s	19.622ms	50	50	100.00
V2	otp_macro_errors	otp_ctrl_macro_errs	50.870s	2.676ms	50	50	100.00
V2	test_access	otp_ctrl_test_access	52.670s	1.770ms	50	50	100.00
V2	stress_all	otp_ctrl_stress_all	5.475m	39.834ms	50	50	100.00
V2	intr_test	otp_ctrl_intr_test	3.490s	571.947us	50	50	100.00
V2	alert_test	otp_ctrl_alert_test	7.930s	387.983us	50	50	100.00
V2	tl_d_oob_addr_access	otp_ctrl_tl_errors	10.940s	2.403ms	20	20	100.00
V2	tl_d_illegal_access	otp_ctrl_tl_errors	10.940s	2.403ms	20	20	100.00
V2	tl_d_outstanding_access	otp_ctrl_csr_hw_reset	4.880s	1.606ms	5	5	100.00
		otp_ctrl_csr_rw	4.690s	682.370us	20	20	100.00
		otp_ctrl_csr_aliasing	8.880s	307.190us	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.880s	822.643us	20	20	100.00
V2	tl_d_partial_access	otp_ctrl_csr_hw_reset	4.880s	1.606ms	5	5	100.00
		otp_ctrl_csr_rw	4.690s	682.370us	20	20	100.00
		otp_ctrl_csr_aliasing	8.880s	307.190us	5	5	100.00
		otp_ctrl_same_csr_outstanding	5.880s	822.643us	20	20	100.00
V2		TOTAL			1101	1101	100.00
V2S	sec_cm_additional_check	otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
V2S	tl_intg_err	otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
		otp_ctrl_tl_intg_err	31.450s	2.659ms	20	20	100.00
V2S	prim_count_check	otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
V2S	prim_fsm_check	otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
V2S	sec_cm_bus_integrity	otp_ctrl_tl_intg_err	31.450s	2.659ms	20	20	100.00
V2S	sec_cm_secret_mem_scramble	otp_ctrl_smoke	18.590s	7.791ms	50	50	100.00
V2S	sec_cm_part_mem_digest	otp_ctrl_smoke	18.590s	7.791ms	50	50	100.00
V2S	sec_cm_dai_fsm_sparse	otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
V2S	sec_cm_kdi_fsm_sparse	otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
V2S	sec_cm_lci_fsm_sparse	otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
V2S	sec_cm_part_fsm_sparse	otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
V2S	sec_cm_scrmbl_fsm_sparse	otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
V2S	sec_cm_timer_fsm_sparse	otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
V2S	sec_cm_dai_ctr_redun	otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
V2S	sec_cm_kdi_seed_ctr_redun	otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
V2S	sec_cm_kdi_entropy_ctr_redun	otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
V2S	sec_cm_lci_ctr_redun	otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
V2S	sec_cm_part_ctr_redun	otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
V2S	sec_cm_scrmbl_ctr_redun	otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
V2S	sec_cm_timer_integ_ctr_redun	otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
V2S	sec_cm_timer_cnsty_ctr_redun	otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
V2S	sec_cm_timer_lfsr_redun	otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
V2S	sec_cm_dai_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.770s	10.590ms	200	200	100.00
		otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
V2S	sec_cm_lci_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.770s	10.590ms	200	200	100.00
V2S	sec_cm_kdi_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.770s	10.590ms	200	200	100.00
V2S	sec_cm_part_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.770s	10.590ms	200	200	100.00
		otp_ctrl_macro_errs	50.870s	2.676ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.770s	10.590ms	200	200	100.00
V2S	sec_cm_timer_fsm_local_esc	otp_ctrl_parallel_lc_esc	28.770s	10.590ms	200	200	100.00
		otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
V2S	sec_cm_dai_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.770s	10.590ms	200	200	100.00
		otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
V2S	sec_cm_lci_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.770s	10.590ms	200	200	100.00
V2S	sec_cm_kdi_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.770s	10.590ms	200	200	100.00
V2S	sec_cm_part_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.770s	10.590ms	200	200	100.00
		otp_ctrl_macro_errs	50.870s	2.676ms	50	50	100.00
V2S	sec_cm_scrmbl_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.770s	10.590ms	200	200	100.00
V2S	sec_cm_timer_fsm_global_esc	otp_ctrl_parallel_lc_esc	28.770s	10.590ms	200	200	100.00
		otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
V2S	sec_cm_part_data_reg_integrity	otp_ctrl_init_fail	13.430s	2.873ms	300	300	100.00
V2S	sec_cm_part_data_reg_bkgn_chk	otp_ctrl_check_fail	58.300s	4.225ms	50	50	100.00
V2S	sec_cm_part_mem_regren	otp_ctrl_dai_lock	48.100s	13.759ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unreadable	otp_ctrl_dai_lock	48.100s	13.759ms	50	50	100.00
V2S	sec_cm_part_mem_sw_unwritable	otp_ctrl_dai_lock	48.100s	13.759ms	50	50	100.00
V2S	sec_cm_lc_part_mem_sw_noaccess	otp_ctrl_dai_lock	48.100s	13.759ms	50	50	100.00
V2S	sec_cm_access_ctrl_mubi	otp_ctrl_dai_lock	48.100s	13.759ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	otp_ctrl_smoke	18.590s	7.791ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	otp_ctrl_dai_lock	48.100s	13.759ms	50	50	100.00
V2S	sec_cm_test_bus_lc_gated	otp_ctrl_smoke	18.590s	7.791ms	50	50	100.00
V2S	sec_cm_test_tl_lc_gate_fsm_sparse	otp_ctrl_sec_cm	4.386m	172.926ms	5	5	100.00
V2S	sec_cm_direct_access_config_regwen	otp_ctrl_regwen	20.340s	5.258ms	50	50	100.00
V2S	sec_cm_check_trigger_config_regwen	otp_ctrl_smoke	18.590s	7.791ms	50	50	100.00
V2S	sec_cm_check_config_regwen	otp_ctrl_smoke	18.590s	7.791ms	50	50	100.00
V2S	sec_cm_macro_mem_integrity	otp_ctrl_macro_errs	50.870s	2.676ms	50	50	100.00
V2S		TOTAL			25	25	100.00
V3	otp_ctrl_low_freq_read	otp_ctrl_low_freq_read	23.520s	7.298ms	1	1	100.00
V3	stress_all_with_rand_reset	otp_ctrl_stress_all_with_rand_reset	3.588m	37.441ms	57	100	57.00
V3		TOTAL			58	101	57.43
		TOTAL			1299	1343	96.72

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	17	17	17	100.00
V2S	2	2	2	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.20	93.73	97.18	95.91	92.53	97.45	96.37	93.21

Failure Buckets

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* has 21 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 21 failures.

    • 0.otp_ctrl_stress_all_with_rand_reset.60484949424281570141033019641522616963444242428264438925734982621267296293689
      Line 86394, in log /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 13623793530 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2243325556 [0x85b66e74] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 13623793530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.otp_ctrl_stress_all_with_rand_reset.97117132213318865101558747429355481727169737227708488581485589559349182370171
      Line 9006, in log /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 21489977158 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (725987857 [0x2b45b211] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
        UVM_INFO @ 21489977158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state has 16 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 16 failures.

    • 1.otp_ctrl_stress_all_with_rand_reset.104255294894879328159854494055303237724126473320100175208335916627991352480705
      Line 260, in log /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  69432941 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @  69432941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.otp_ctrl_stress_all_with_rand_reset.21377374855785429332942352741257308057742358372256770993307690756477007855464
      Line 276, in log /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 274517259 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2 [0x2] vs 0 [0x0]) reg name: otp_ctrl_core_reg_block.intr_state
        UVM_INFO @ 274517259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 14 more failures.

• UVM_ERROR (otp_ctrl_base_vseq.sv:217) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr * rdata* readout mismatch has 2 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 2 failures.

    • 56.otp_ctrl_stress_all_with_rand_reset.59829650124085536996778394580413069660494297307879179663420641984467477801861
      Line 83, in log /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/56.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3821951151 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 3172844727 [0xbd1dc4b7]) dai addr 740 rdata0 readout mismatch
        UVM_INFO @ 3821951151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 69.otp_ctrl_stress_all_with_rand_reset.30783054536938846483406629657249845133970212862160549222334796862373662928273
      Line 65507, in log /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/69.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11397264843 ps: (otp_ctrl_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.otp_ctrl_low_freq_read_vseq] Check failed rdata0 == exp_data0 (0 [0x0] vs 2621892144 [0x9c46e630]) dai addr 734 rdata0 readout mismatch
        UVM_INFO @ 11397264843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(cio_test_en_o == *)' has 1 failures:

  • Test otp_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 10.otp_ctrl_csr_mem_rw_with_rand_reset.105441963923042753739461772404331768823159389206925569085924084985964931380350
      Line 80, in log /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(cio_test_en_o == 0)'
        UVM_ERROR @  85254847 ps: (otp_ctrl_if.sv:294) [ASSERT FAILED] CioTestEnOWithDftOff_A
        UVM_INFO @  85254847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:1132) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_regwen has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 19.otp_ctrl_stress_all_with_rand_reset.14213147100372083706603167899311445155090362913217725602412351196216068509190
      Line 8934, in log /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1636064220 ps: (otp_ctrl_scoreboard.sv:1132) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 1 [0x1]) reg name: otp_ctrl_core_reg_block.direct_access_regwen
        UVM_INFO @ 1636064220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:867) [otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 30.otp_ctrl_stress_all_with_rand_reset.24822361143293925316423713853342556263957241801575290276506479494101844427638
      Line 18841, in log /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 43262712981 ps: (cip_base_vseq.sv:867) [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 43262712981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 93.otp_ctrl_stress_all_with_rand_reset.89418201728764221459056461931541359297623674860470205373957144232856973857372
      Line 29487, in log /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/93.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 18343809264 ps: (otp_ctrl_scoreboard.sv:277) [uvm_test_top.env.scoreboard] Check failed exp_alert != OtpNoAlert (0 [0x0] vs 0 [0x0])
        UVM_INFO @ 18343809264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=171) has 1 failures:

  • Test otp_ctrl_stress_all_with_rand_reset has 1 failures.

    • 99.otp_ctrl_stress_all_with_rand_reset.98248118829153360557611023196127339659674612078562880199145940420678168496483
      Line 22634, in log /workspaces/repo/scratch/os_regression_2024_10_08/otp_ctrl-sim-vcs/99.otp_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 52433593441 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout otp_ctrl_core_reg_block.status.check_pending (addr=0x2b053010, Comparison=CompareOpEq, exp_data=0x0, call_count=171)
        UVM_INFO @ 52433593441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.10.04_00.42.49
• 2024.09.25_11.01.49
• 2024.09.19_09.05.36
• 2024.09.12_10.17.11
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