748235cbb6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 9.000s | 192.840us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 2.000s | 47.486us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 7.000s | 64.470us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 6.000s | 491.811us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 3.000s | 21.788us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 4.000s | 13.707us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 7.000s | 64.470us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 3.000s | 21.788us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 2.900m | 15.176ms | 50 | 50 | 100.00 |
| V2 | cnt_rollover | cnt_rollover | 1.800m | 2.715ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 9.000s | 31.624us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.950m | 4.033ms | 50 | 50 | 100.00 |
| V2 | alert_test | pattgen_alert_test | 7.000s | 14.721us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 4.000s | 52.323us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 5.000s | 408.347us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 5.000s | 408.347us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 2.000s | 47.486us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 7.000s | 64.470us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 3.000s | 21.788us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 4.000s | 15.568us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 2.000s | 47.486us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 7.000s | 64.470us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 3.000s | 21.788us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 4.000s | 15.568us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 340 | 340 | 100.00 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 4.000s | 117.521us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 3.000s | 240.444us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 4.000s | 117.521us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 40.733m | 225.574ms | 44 | 50 | 88.00 |
| V3 | TOTAL | 44 | 50 | 88.00 | |||
| TOTAL | 514 | 520 | 98.85 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 8 | 8 | 8 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.79 | 100.00 | 100.00 | 100.00 | 99.06 | 96.13 | -- | 100.00 | 90.43 |
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 6 failures:
4.pattgen_stress_all_with_rand_reset.84746161221956509119199493461585299162731085437207565427048820010509218434689
Line 1603, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 812906187951 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
8.pattgen_stress_all_with_rand_reset.5746508062903354488978534455703644798706553473504295899300623742697745232135
Line 1602, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/8.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 261601286203 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
... and 4 more failures.