PATTGEN Simulation Results

Wednesday February 14 2024 20:02:28 UTC

GitHub Revision: `93b7cb99d8`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 53669536132820869698500732458181248593474076177124168900566436467251403141328

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	8.000s	599.563us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	77.933us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	44.506us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	139.471us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	30.428us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	6.000s	54.949us	2	20	10.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	44.506us	20	20	100.00
		pattgen_csr_aliasing	3.000s	30.428us	5	5	100.00
V1		TOTAL			87	105	82.86
V2	perf	pattgen_perf	2.767m	5.888ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.833m	2.632ms	50	50	100.00
V2	error	pattgen_error	7.000s	123.985us	50	50	100.00
V2	stress_all	pattgen_stress_all	5.200m	31.764ms	50	50	100.00
V2	alert_test	pattgen_alert_test	8.000s	15.268us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	32.966us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	104.462us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	104.462us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	77.933us	5	5	100.00
		pattgen_csr_rw	2.000s	44.506us	20	20	100.00
		pattgen_csr_aliasing	3.000s	30.428us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	59.454us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	77.933us	5	5	100.00
		pattgen_csr_rw	2.000s	44.506us	20	20	100.00
		pattgen_csr_aliasing	3.000s	30.428us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	59.454us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	330.067us	20	20	100.00
		pattgen_sec_cm	2.000s	58.310us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	330.067us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	46.567m	135.544ms	5	50	10.00
V3		TOTAL			5	50	10.00
		TOTAL			457	520	87.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:757) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.

has 61 failures:

Test pattgen_csr_mem_rw_with_rand_reset has 18 failures.

0.pattgen_csr_mem_rw_with_rand_reset.98796957300956651632208317773699495861073289370571259323558031047789408468485
Line 278, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @  14133787 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_ERROR @  14139876 ps: (cip_base_vseq.sv:715) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  14139876 ps: (cip_base_vseq.sv:718) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/1
  UVM_INFO @  14232657 ps: (cip_base_vseq.sv:726) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_csr_mem_rw_with_rand_reset.20163169634469605531021879504171684128649830262321844941078508570815236275231
Line 278, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @  32156133 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_ERROR @  32174323 ps: (cip_base_vseq.sv:715) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  32174323 ps: (cip_base_vseq.sv:718) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/1
  UVM_INFO @  32337587 ps: (cip_base_vseq.sv:726) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 16 more failures.

Test pattgen_stress_all_with_rand_reset has 43 failures.

1.pattgen_stress_all_with_rand_reset.16093250964996227413674361022169915338252359584878105699906829764547942690236
Line 293, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  29855236 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_ERROR @  29870888 ps: (cip_base_vseq.sv:715) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  29870888 ps: (cip_base_vseq.sv:718) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @  29986274 ps: (cip_base_vseq.sv:726) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.10082580398641649782963604840729671616714458228760582879794595941716700000000
Line 397, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 17747136341 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_ERROR @ 17747150702 ps: (cip_base_vseq.sv:715) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 17747150702 ps: (cip_base_vseq.sv:718) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 17747313966 ps: (cip_base_vseq.sv:726) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 41 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 4.pattgen_stress_all_with_rand_reset.73667226012718675097823996418118734193144925367346217377317581656209728026170
    Line 396, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3611171282 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 9.pattgen_stress_all_with_rand_reset.62137000922447035028125460617087132067711810279865518544583671551501261292041
    Line 334, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/9.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6001620521 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```