PATTGEN Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: 17d5a97c3b

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	12.000s	1.312ms	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	89.487us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	16.965us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	63.355us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	14.944us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	6.000s	75.928us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	16.965us	20	20	100.00
		pattgen_csr_aliasing	3.000s	14.944us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.750m	4.071ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.933m	10.529ms	49	50	98.00
V2	error	pattgen_error	7.000s	60.927us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.767m	25.310ms	50	50	100.00
V2	alert_test	pattgen_alert_test	9.000s	16.498us	50	50	100.00
V2	intr_test	pattgen_intr_test	8.000s	28.737us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	8.000s	158.216us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	8.000s	158.216us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	89.487us	5	5	100.00
		pattgen_csr_rw	4.000s	16.965us	20	20	100.00
		pattgen_csr_aliasing	3.000s	14.944us	5	5	100.00
		pattgen_same_csr_outstanding	8.000s	130.698us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	89.487us	5	5	100.00
		pattgen_csr_rw	4.000s	16.965us	20	20	100.00
		pattgen_csr_aliasing	3.000s	14.944us	5	5	100.00
		pattgen_same_csr_outstanding	8.000s	130.698us	20	20	100.00
V2		TOTAL			339	340	99.71
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	166.482us	20	20	100.00
		pattgen_sec_cm	2.000s	293.154us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	166.482us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	41.583m	414.627ms	46	50	92.00
V3		TOTAL			46	50	92.00
		TOTAL			515	520	99.04

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	7	87.50
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.79	100.00	100.00	100.00	99.06	96.13	--	100.00	90.43

Failure Buckets

• UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 4 failures:
  • Test pattgen_stress_all_with_rand_reset has 4 failures.

    • 1.pattgen_stress_all_with_rand_reset.88327003674426148292702690796962090284306538188593224878514962908426164616270
      Line 575, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 42289103851 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
        --> channel 1 item mismatch!
        --> EXP:
        ------------------------------------
        Name      Type          Size  Value
      

    • 36.pattgen_stress_all_with_rand_reset.58082550697275844986093692031782971690635263074602046762554501511574886958155
      Line 533, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/36.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17690242309 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
        --> channel 0 item mismatch!
        --> EXP:
        ------------------------------------
        Name      Type          Size  Value
      

    • ... and 2 more failures.

• Job pattgen-sim-xcelium_run_default killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:
  • Test cnt_rollover has 1 failures.

    • 14.cnt_rollover.50976313734803559062730417752366408041729616848540644508565817361113395925747
      Log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/14.cnt_rollover/latest/run.log

        Job ID: smart:2e752666-38ad-476b-b294-6e430af7e181
      

Past Results

• Latest
• lint
• 2024.01.22_11.02.37
• 2024.01.18_08.42.10
• 2024.01.15_03.59.34
• 2024.01.11_03.13.38
• 2024.01.08_03.00.27
• 2024.01.04_01.24.49