4d88b9516c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 6.000s | 381.033us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 3.000s | 104.827us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 3.000s | 25.297us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 5.000s | 515.009us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 5.000s | 51.853us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 4.000s | 44.484us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 3.000s | 25.297us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 5.000s | 51.853us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 1.767m | 2.691ms | 50 | 50 | 100.00 |
| V2 | cnt_rollover | cnt_rollover | 1.900m | 2.690ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 4.000s | 129.542us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 4.300m | 47.504ms | 50 | 50 | 100.00 |
| V2 | alert_test | pattgen_alert_test | 4.000s | 21.133us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 7.000s | 11.277us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 6.000s | 407.174us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 6.000s | 407.174us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 3.000s | 104.827us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 3.000s | 25.297us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 5.000s | 51.853us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 3.000s | 21.589us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 3.000s | 104.827us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 3.000s | 25.297us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 5.000s | 51.853us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 3.000s | 21.589us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 340 | 340 | 100.00 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 4.000s | 308.048us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 3.000s | 280.917us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 4.000s | 308.048us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 50.100m | 304.823ms | 44 | 50 | 88.00 |
| V3 | TOTAL | 44 | 50 | 88.00 | |||
| TOTAL | 514 | 520 | 98.85 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 8 | 8 | 8 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.79 | 100.00 | 100.00 | 100.00 | 99.06 | 96.13 | -- | 100.00 | 90.43 |
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 6 failures:
11.pattgen_stress_all_with_rand_reset.99274757492323101797116621777869638459890683155428490997686696332043319191719
Line 497, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/11.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 68591418767 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
-------------------------------------
Name Type Size Value
16.pattgen_stress_all_with_rand_reset.16941998070771488476037512004220553207393488700411242583627459863396745329912
Line 849, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/16.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 300846285570 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
... and 4 more failures.