0dd29ab736| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 4.000s | 271.313us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 2.000s | 83.676us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 3.000s | 40.684us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 5.000s | 621.691us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 3.000s | 14.875us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 3.000s | 21.710us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 3.000s | 40.684us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 3.000s | 14.875us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 1.850m | 10.970ms | 50 | 50 | 100.00 |
| V2 | cnt_rollover | cnt_rollover | 1.783m | 5.151ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 3.000s | 45.086us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 4.900m | 14.491ms | 50 | 50 | 100.00 |
| V2 | alert_test | pattgen_alert_test | 4.000s | 14.925us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 3.000s | 48.107us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 5.000s | 379.681us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 5.000s | 379.681us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 2.000s | 83.676us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 3.000s | 40.684us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 3.000s | 14.875us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 3.000s | 19.241us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 2.000s | 83.676us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 3.000s | 40.684us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 3.000s | 14.875us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 3.000s | 19.241us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 340 | 340 | 100.00 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 4.000s | 273.799us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 3.000s | 88.796us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 4.000s | 273.799us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 29.767m | 264.140ms | 43 | 50 | 86.00 |
| V3 | TOTAL | 43 | 50 | 86.00 | |||
| TOTAL | 513 | 520 | 98.65 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 8 | 8 | 8 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.79 | 100.00 | 100.00 | 100.00 | 99.06 | 96.13 | -- | 100.00 | 90.43 |
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 7 failures:
8.pattgen_stress_all_with_rand_reset.3649476712933033102147207488399340173431047281874995092463638700705174074346
Line 329, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/8.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1157465342 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
12.pattgen_stress_all_with_rand_reset.10613709207954224632831020057908130283925879531001312869014208446080151812840
Line 455, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/12.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 36775824473 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
... and 5 more failures.