PATTGEN Simulation Results

Wednesday January 31 2024 20:02:52 UTC

GitHub Revision: 4ddd81322f

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 21932966400645871531253577545734825173576945735198195365995401811578215479543

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pattgen_smoke 0 50 0.00
V1 csr_hw_reset pattgen_csr_hw_reset 0 5 0.00
V1 csr_rw pattgen_csr_rw 0 20 0.00
V1 csr_bit_bash pattgen_csr_bit_bash 0 5 0.00
V1 csr_aliasing pattgen_csr_aliasing 0 5 0.00
V1 csr_mem_rw_with_rand_reset pattgen_csr_mem_rw_with_rand_reset 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr pattgen_csr_rw 0 20 0.00
pattgen_csr_aliasing 0 5 0.00
V1 TOTAL 0 105 0.00
V2 perf pattgen_perf 0 50 0.00
V2 cnt_rollover cnt_rollover 0 50 0.00
V2 error pattgen_error 0 50 0.00
V2 stress_all pattgen_stress_all 0 50 0.00
V2 alert_test pattgen_alert_test 0 50 0.00
V2 intr_test pattgen_intr_test 0 50 0.00
V2 tl_d_oob_addr_access pattgen_tl_errors 0 20 0.00
V2 tl_d_illegal_access pattgen_tl_errors 0 20 0.00
V2 tl_d_outstanding_access pattgen_csr_hw_reset 0 5 0.00
pattgen_csr_rw 0 20 0.00
pattgen_csr_aliasing 0 5 0.00
pattgen_same_csr_outstanding 0 20 0.00
V2 tl_d_partial_access pattgen_csr_hw_reset 0 5 0.00
pattgen_csr_rw 0 20 0.00
pattgen_csr_aliasing 0 5 0.00
pattgen_same_csr_outstanding 0 20 0.00
V2 TOTAL 0 340 0.00
V2S tl_intg_err pattgen_tl_intg_err 0 20 0.00
pattgen_sec_cm 0 5 0.00
V2S sec_cm_bus_integrity pattgen_tl_intg_err 0 20 0.00
V2S TOTAL 0 25 0.00
V3 stress_all_with_rand_reset pattgen_stress_all_with_rand_reset 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 0 520 0.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 0 0.00
V2 8 8 0 0.00
V2S 2 2 0 0.00
V3 1 1 0 0.00

Failure Buckets

Past Results