796f9fb805| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 9.000s | 166.553us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 2.000s | 189.849us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 3.000s | 60.360us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 5.000s | 197.427us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 2.000s | 27.259us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 3.000s | 454.397us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 3.000s | 60.360us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 2.000s | 27.259us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 2.933m | 4.114ms | 50 | 50 | 100.00 |
| V2 | cnt_rollover | cnt_rollover | 1.867m | 2.464ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 5.000s | 23.965us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 2.850m | 4.102ms | 50 | 50 | 100.00 |
| V2 | alert_test | pattgen_alert_test | 4.000s | 23.766us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 3.000s | 25.407us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 5.000s | 202.383us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 5.000s | 202.383us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 2.000s | 189.849us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 3.000s | 60.360us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 2.000s | 27.259us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 3.000s | 186.009us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 2.000s | 189.849us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 3.000s | 60.360us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 2.000s | 27.259us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 3.000s | 186.009us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 340 | 340 | 100.00 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 3.000s | 528.759us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 5.000s | 61.558us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 3.000s | 528.759us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 42.417m | 214.456ms | 46 | 50 | 92.00 |
| V3 | TOTAL | 46 | 50 | 92.00 | |||
| TOTAL | 516 | 520 | 99.23 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 8 | 8 | 8 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.79 | 100.00 | 100.00 | 100.00 | 99.06 | 96.13 | -- | 100.00 | 90.43 |
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 4 failures:
6.pattgen_stress_all_with_rand_reset.63142007650112514314797373112293816199420904479895771715412007506338175159218
Line 764, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/6.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 86846848134 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
-------------------------------------
Name Type Size Value
12.pattgen_stress_all_with_rand_reset.49378342855200053596130154215205211406666273674619630806145359809492516963267
Line 601, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/12.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12678678439 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 0 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
... and 2 more failures.