PATTGEN Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: `8faf04697a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	772.820us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	7.000s	101.363us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	7.000s	43.899us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	770.308us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	8.000s	15.423us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	9.000s	105.857us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	7.000s	43.899us	20	20	100.00
		pattgen_csr_aliasing	8.000s	15.423us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.000m	5.377ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	2.000m	2.660ms	50	50	100.00
V2	error	pattgen_error	3.000s	28.008us	50	50	100.00
V2	stress_all	pattgen_stress_all	1.983m	2.784ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	45.601us	50	50	100.00
V2	intr_test	pattgen_intr_test	12.000s	14.519us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	13.000s	23.185us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	13.000s	23.185us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	7.000s	101.363us	5	5	100.00
		pattgen_csr_rw	7.000s	43.899us	20	20	100.00
		pattgen_csr_aliasing	8.000s	15.423us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	46.076us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	7.000s	101.363us	5	5	100.00
		pattgen_csr_rw	7.000s	43.899us	20	20	100.00
		pattgen_csr_aliasing	8.000s	15.423us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	46.076us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	7.000s	44.602us	20	20	100.00
		pattgen_sec_cm	2.000s	143.069us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	7.000s	44.602us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	30.533m	176.571ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			484	520	93.08

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:757) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.

has 27 failures:

Test pattgen_stress_all_with_rand_reset has 27 failures.

0.pattgen_stress_all_with_rand_reset.45320957683196354866140043491268004501067347061603523264942228183846757143917
Line 342, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9423682911 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_ERROR @ 9423690000 ps: (cip_base_vseq.sv:715) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 9423690000 ps: (cip_base_vseq.sv:718) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @ 9423794165 ps: (cip_base_vseq.sv:726) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.49622608755718463702023999760970963405880063562950394222591889201474251360153
Line 592, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 69297212279 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_ERROR @ 69297236507 ps: (cip_base_vseq.sv:715) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 69297236507 ps: (cip_base_vseq.sv:718) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 4/10
  UVM_INFO @ 69297410419 ps: (cip_base_vseq.sv:726) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 25 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 5 failures:
- Test pattgen_stress_all_with_rand_reset has 5 failures.
  - 2.pattgen_stress_all_with_rand_reset.16334671135500974084979845310902805321195684494525779484674441844371289208073
    Line 476, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 39896295292 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 10.pattgen_stress_all_with_rand_reset.51432774761630461509362760805270082262556764837714252080877268370714928483417
    Line 739, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/10.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 37274440196 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:715) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.

has 3 failures:

Test pattgen_stress_all_with_rand_reset has 3 failures.

19.pattgen_stress_all_with_rand_reset.96793266634629909595699559708885125800296642911280207101810110112330969725468
Line 308, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/19.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  97495334 ps: (cip_base_vseq.sv:715) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  97495334 ps: (cip_base_vseq.sv:718) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/5
  UVM_INFO @  97610720 ps: (cip_base_vseq.sv:726) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Stress w/ reset is done for run 2/5

43.pattgen_stress_all_with_rand_reset.9065811642064724369452551770190724324753147217046094666117910711541591700778
Line 290, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/43.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 135194383 ps: (cip_base_vseq.sv:715) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 135194383 ps: (cip_base_vseq.sv:718) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 135527719 ps: (cip_base_vseq.sv:726) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Stress w/ reset is done for run 1/10

... and 1 more failures.

UVM_ERROR (pattgen_scoreboard.sv:249) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all_with_rand_reset has 1 failures.
  - 8.pattgen_stress_all_with_rand_reset.73740087867848536313648595921179306449188943377859664340771805026057475143790
    Line 1391, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/8.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 58909120030 ps: (pattgen_scoreboard.sv:249) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  ------------------------------------
  Name      Type          Size  Value
  ------------------------------------
  exp_item  pattgen_item  -     @21577
```