PATTGEN Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: `df66f8a42e`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	10.000s	787.071us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	14.418us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	15.355us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	38.963us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	16.032us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	23.230us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	15.355us	20	20	100.00
		pattgen_csr_aliasing	3.000s	16.032us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.950m	11.444ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.767m	3.174ms	50	50	100.00
V2	error	pattgen_error	6.000s	32.830us	50	50	100.00
V2	stress_all	pattgen_stress_all	4.467m	13.502ms	50	50	100.00
V2	alert_test	pattgen_alert_test	6.000s	37.265us	50	50	100.00
V2	intr_test	pattgen_intr_test	5.000s	11.433us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	189.472us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	189.472us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	14.418us	5	5	100.00
		pattgen_csr_rw	4.000s	15.355us	20	20	100.00
		pattgen_csr_aliasing	3.000s	16.032us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	127.157us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	14.418us	5	5	100.00
		pattgen_csr_rw	4.000s	15.355us	20	20	100.00
		pattgen_csr_aliasing	3.000s	16.032us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	127.157us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	266.258us	20	20	100.00
		pattgen_sec_cm	4.000s	60.268us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	266.258us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	30.467m	633.244ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			486	520	93.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:775) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.

has 31 failures:

Test pattgen_stress_all_with_rand_reset has 31 failures.

1.pattgen_stress_all_with_rand_reset.43515075932021649902148662454517386611066616566271349656401012108840848134935
Line 419, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7267213973 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_ERROR @ 7267224510 ps: (cip_base_vseq.sv:720) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 7267224510 ps: (cip_base_vseq.sv:723) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/5
  UVM_INFO @ 7267343560 ps: (cip_base_vseq.sv:731) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.113287793258666635330227125431439049876675175081758606373243403290463312072183
Line 519, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 13329347798 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_ERROR @ 13329356606 ps: (cip_base_vseq.sv:720) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 13329356606 ps: (cip_base_vseq.sv:723) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/10
  UVM_INFO @ 13329458646 ps: (cip_base_vseq.sv:731) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 29 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 3 failures:
- Test pattgen_stress_all_with_rand_reset has 3 failures.
  - 32.pattgen_stress_all_with_rand_reset.90242246827866298597547908462180021581090563014527172877783718806728816182029
    Line 320, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/32.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 412553596 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - 46.pattgen_stress_all_with_rand_reset.59819507830681293033742770634918238064858522410544559246864416525434630906382
    Line 785, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/46.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 35230448139 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 1 more failures.