PATTGEN Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: `49a27e136c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	18.000s	79.539us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	9.000s	102.651us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	8.000s	46.934us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	11.000s	513.948us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	5.000s	27.970us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	12.000s	24.907us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	8.000s	46.934us	20	20	100.00
		pattgen_csr_aliasing	5.000s	27.970us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.950m	16.450ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	2.117m	2.633ms	50	50	100.00
V2	error	pattgen_error	17.000s	32.703us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.033m	10.700ms	50	50	100.00
V2	alert_test	pattgen_alert_test	18.000s	13.185us	50	50	100.00
V2	intr_test	pattgen_intr_test	20.000s	14.206us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	16.000s	30.544us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	16.000s	30.544us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	9.000s	102.651us	5	5	100.00
		pattgen_csr_rw	8.000s	46.934us	20	20	100.00
		pattgen_csr_aliasing	5.000s	27.970us	5	5	100.00
		pattgen_same_csr_outstanding	11.000s	25.428us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	9.000s	102.651us	5	5	100.00
		pattgen_csr_rw	8.000s	46.934us	20	20	100.00
		pattgen_csr_aliasing	5.000s	27.970us	5	5	100.00
		pattgen_same_csr_outstanding	11.000s	25.428us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	13.000s	736.598us	20	20	100.00
		pattgen_sec_cm	10.000s	73.435us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	13.000s	736.598us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	28.417m	132.949ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			481	520	92.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:775) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.

has 34 failures:

Test pattgen_stress_all_with_rand_reset has 34 failures.

2.pattgen_stress_all_with_rand_reset.38421739422499227684943439667411483781816470904929955315610747132301389989276
Line 391, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6008764339 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_ERROR @ 6008765261 ps: (cip_base_vseq.sv:720) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 6008765261 ps: (cip_base_vseq.sv:723) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/5
  UVM_INFO @ 6008785261 ps: (cip_base_vseq.sv:731) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

3.pattgen_stress_all_with_rand_reset.113097901474321022771392698406908319746360809118311422619861572140058249891267
Line 456, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 123125858258 ps: (cip_base_vseq.sv:775) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited too long to issue a reset with no outstanding accesses.
  UVM_ERROR @ 123125952064 ps: (cip_base_vseq.sv:720) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 123125952064 ps: (cip_base_vseq.sv:723) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 4/10
  UVM_INFO @ 123126752064 ps: (cip_base_vseq.sv:731) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 32 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 5 failures:
- Test pattgen_stress_all_with_rand_reset has 5 failures.
  - 0.pattgen_stress_all_with_rand_reset.65190686192227906412452548750253644084255288677514100681416497120190047568730
    Line 448, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9406526829 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 11.pattgen_stress_all_with_rand_reset.29882958997182250222731918734067440828596012545746528782855821153930528533022
    Line 663, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/11.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 313618710856 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 3 more failures.