PATTGEN Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: `e0c4026501`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	15.000s	1.314ms	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	5.000s	14.364us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	5.000s	35.116us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	967.104us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	5.000s	18.011us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	5.000s	113.481us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	5.000s	35.116us	20	20	100.00
		pattgen_csr_aliasing	5.000s	18.011us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.933m	5.310ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.900m	2.633ms	50	50	100.00
V2	error	pattgen_error	4.000s	229.541us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.883m	8.123ms	50	50	100.00
V2	alert_test	pattgen_alert_test	7.000s	16.384us	50	50	100.00
V2	intr_test	pattgen_intr_test	4.000s	13.292us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	130.408us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	130.408us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	5.000s	14.364us	5	5	100.00
		pattgen_csr_rw	5.000s	35.116us	20	20	100.00
		pattgen_csr_aliasing	5.000s	18.011us	5	5	100.00
		pattgen_same_csr_outstanding	5.000s	17.996us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	5.000s	14.364us	5	5	100.00
		pattgen_csr_rw	5.000s	35.116us	20	20	100.00
		pattgen_csr_aliasing	5.000s	18.011us	5	5	100.00
		pattgen_same_csr_outstanding	5.000s	17.996us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	94.075us	20	20	100.00
		pattgen_sec_cm	5.000s	100.382us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	94.075us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	31.700m	83.766ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			484	520	93.08

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:789) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 32 failures:

Test pattgen_stress_all_with_rand_reset has 32 failures.

0.pattgen_stress_all_with_rand_reset.18677045403269002627495063277751640249419105491988445706152334690020558449879
Line 309, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 306055644 ps: (cip_base_vseq.sv:789) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 306056476 ps: (cip_base_vseq.sv:720) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 306056476 ps: (cip_base_vseq.sv:723) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 306127183 ps: (cip_base_vseq.sv:731) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.111773423308420601216692287057168008313713265175503622835156783025352412617777
Line 1030, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 547936220117 ps: (cip_base_vseq.sv:789) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 547936242707 ps: (cip_base_vseq.sv:720) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 547936242707 ps: (cip_base_vseq.sv:723) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 8/10
  UVM_INFO @ 547936867707 ps: (cip_base_vseq.sv:731) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 30 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 4 failures:
- Test pattgen_stress_all_with_rand_reset has 4 failures.
  - 9.pattgen_stress_all_with_rand_reset.78809594612175192276444128510521613522452497283340479217186537885854376445248
    Line 1418, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/9.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 84427781867 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 16.pattgen_stress_all_with_rand_reset.4227358182589540361032442854049161827726172347593913000518689867420952751918
    Line 303, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/16.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 590622278 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 2 more failures.