PATTGEN Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: `0cdf265eaa`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	16.000s	25.832us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	16.309us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	32.770us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	198.870us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	37.406us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	12.000s	40.631us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	32.770us	20	20	100.00
		pattgen_csr_aliasing	3.000s	37.406us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.800m	4.156ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.783m	2.660ms	50	50	100.00
V2	error	pattgen_error	12.000s	54.568us	50	50	100.00
V2	stress_all	pattgen_stress_all	4.467m	6.947ms	50	50	100.00
V2	alert_test	pattgen_alert_test	21.000s	99.607us	50	50	100.00
V2	intr_test	pattgen_intr_test	6.000s	38.400us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	13.000s	156.977us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	13.000s	156.977us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	16.309us	5	5	100.00
		pattgen_csr_rw	3.000s	32.770us	20	20	100.00
		pattgen_csr_aliasing	3.000s	37.406us	5	5	100.00
		pattgen_same_csr_outstanding	8.000s	72.371us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	16.309us	5	5	100.00
		pattgen_csr_rw	3.000s	32.770us	20	20	100.00
		pattgen_csr_aliasing	3.000s	37.406us	5	5	100.00
		pattgen_same_csr_outstanding	8.000s	72.371us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	8.000s	43.607us	20	20	100.00
		pattgen_sec_cm	7.000s	78.963us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	8.000s	43.607us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	34.283m	569.119ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			481	520	92.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:816) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 31 failures:

Test pattgen_stress_all_with_rand_reset has 31 failures.

0.pattgen_stress_all_with_rand_reset.81536854427548163039111661219765137936122727095537350390441868086185080196571
Line 312, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1748620715 ps: (cip_base_vseq.sv:816) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1748623309 ps: (cip_base_vseq.sv:742) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1748623309 ps: (cip_base_vseq.sv:745) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @ 1748763309 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.4714515642077769098813465400292463499557941654066343715925350824175530508212
Line 476, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 33683361491 ps: (cip_base_vseq.sv:816) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 33683378031 ps: (cip_base_vseq.sv:742) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 33683378031 ps: (cip_base_vseq.sv:745) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/10
  UVM_INFO @ 33683524371 ps: (cip_base_vseq.sv:753) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 29 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 8 failures:
- Test pattgen_stress_all_with_rand_reset has 8 failures.
  - 8.pattgen_stress_all_with_rand_reset.78324878473416720757260662702611062661303351448799784052970825901511438896555
    Line 705, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/8.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 52402048751 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 15.pattgen_stress_all_with_rand_reset.11167061060997435201982575536500917992026301519057881456081259704893356898458
    Line 303, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/15.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  72109906 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 6 more failures.