PATTGEN Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: `d3942ca074`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	10.000s	1.047ms	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	14.863us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	5.000s	31.134us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	280.019us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	7.000s	19.360us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	7.000s	75.972us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	5.000s	31.134us	20	20	100.00
		pattgen_csr_aliasing	7.000s	19.360us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.933m	2.776ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.883m	10.966ms	50	50	100.00
V2	error	pattgen_error	7.000s	706.838us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.667m	4.099ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	46.091us	50	50	100.00
V2	intr_test	pattgen_intr_test	7.000s	17.751us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	4.000s	198.661us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	4.000s	198.661us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	14.863us	5	5	100.00
		pattgen_csr_rw	5.000s	31.134us	20	20	100.00
		pattgen_csr_aliasing	7.000s	19.360us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	118.659us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	14.863us	5	5	100.00
		pattgen_csr_rw	5.000s	31.134us	20	20	100.00
		pattgen_csr_aliasing	7.000s	19.360us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	118.659us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	1.954ms	20	20	100.00
		pattgen_sec_cm	2.000s	120.351us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	1.954ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	40.633m	273.106ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			485	520	93.27

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 33 failures:

Test pattgen_stress_all_with_rand_reset has 33 failures.

0.pattgen_stress_all_with_rand_reset.75172637023948048780624227171301352468303929070896539383752373368125413919515
Line 308, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 805614821 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 805616837 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 805616837 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 805637671 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.16284995303715193702029971588359096462373647335754650428163066274211365139771
Line 460, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 37503777046 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 37503798237 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 37503798237 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/10
  UVM_INFO @ 37504089906 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 31 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 23.pattgen_stress_all_with_rand_reset.61947747866279257348250883356120568478832636047221556315714610317199251541610
    Line 590, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/23.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 112623013691 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 27.pattgen_stress_all_with_rand_reset.44256719952264976796786918824659555304558253474719679517683701528378590690141
    Line 947, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/27.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 189737291413 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```