PATTGEN Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: `2723ca659d`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	634.631us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	44.979us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	51.170us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	282.434us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	96.552us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	82.506us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	51.170us	20	20	100.00
		pattgen_csr_aliasing	3.000s	96.552us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.667m	15.776ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.800m	29.212ms	50	50	100.00
V2	error	pattgen_error	4.000s	227.053us	50	50	100.00
V2	stress_all	pattgen_stress_all	1.867m	2.785ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	41.512us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	50.042us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	357.898us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	357.898us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	44.979us	5	5	100.00
		pattgen_csr_rw	3.000s	51.170us	20	20	100.00
		pattgen_csr_aliasing	3.000s	96.552us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	20.702us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	44.979us	5	5	100.00
		pattgen_csr_rw	3.000s	51.170us	20	20	100.00
		pattgen_csr_aliasing	3.000s	96.552us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	20.702us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	50.741us	20	20	100.00
		pattgen_sec_cm	3.000s	137.620us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	50.741us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	32.417m	335.435ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			483	520	92.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 34 failures:

Test pattgen_stress_all_with_rand_reset has 34 failures.

0.pattgen_stress_all_with_rand_reset.32737945897792898298525234862764180807362073548601618060494702580782902809175
Line 290, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 344985234 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 345013471 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 345013471 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 345142503 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.33701920201802236619605869190443036525799744665010709005779705662129224918395
Line 670, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 45379978886 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 45379982528 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 45379982528 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 5/10
  UVM_INFO @ 45380128359 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 32 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 3 failures:
- Test pattgen_stress_all_with_rand_reset has 3 failures.
  - 5.pattgen_stress_all_with_rand_reset.103783184347207643387540417300002916083208316438935618423923352719031732144561
    Line 318, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/5.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 699701882 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 9.pattgen_stress_all_with_rand_reset.115576576890520210393751028560921814639914343334656409974334502511430440761587
    Line 346, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/9.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5489874088 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 1 more failures.