PATTGEN Simulation Results

Thursday April 11 2024 19:07:25 UTC

GitHub Revision: `1f410ef5dc`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 77676901304510083363507443373754332549719316834151559528665885252978172929472

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	10.000s	349.516us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	27.164us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	36.516us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	285.910us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	92.206us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	69.264us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	36.516us	20	20	100.00
		pattgen_csr_aliasing	3.000s	92.206us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.633m	8.394ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.750m	4.962ms	50	50	100.00
V2	error	pattgen_error	3.000s	42.238us	50	50	100.00
V2	stress_all	pattgen_stress_all	8.267m	12.374ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	13.156us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	19.465us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	243.135us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	243.135us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	27.164us	5	5	100.00
		pattgen_csr_rw	3.000s	36.516us	20	20	100.00
		pattgen_csr_aliasing	3.000s	92.206us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	36.848us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	27.164us	5	5	100.00
		pattgen_csr_rw	3.000s	36.516us	20	20	100.00
		pattgen_csr_aliasing	3.000s	92.206us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	36.848us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	90.182us	20	20	100.00
		pattgen_sec_cm	2.000s	110.249us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	90.182us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	28.533m	69.465ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			485	520	93.27

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 33 failures:

Test pattgen_stress_all_with_rand_reset has 33 failures.

2.pattgen_stress_all_with_rand_reset.36659038258763997069948870780330751844728256302316646841914604523888079738584
Line 343, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 28578509509 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 28578547311 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 28578547311 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @ 28578984811 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

3.pattgen_stress_all_with_rand_reset.65680066920080723005019123616842882334962448584773316132802874244124701150
Line 294, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1338706336 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1338722639 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1338722639 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @ 1338783863 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 31 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 24.pattgen_stress_all_with_rand_reset.13282582536871651669366042911460698290022069052752749561396064890599308412045
    Line 532, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/24.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14017863128 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 45.pattgen_stress_all_with_rand_reset.52266953476050274949557413511077769277593139925208362139540831980808446770277
    Line 464, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/45.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 42820242182 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```