PATTGEN Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: `9f4903e77a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	8.000s	155.476us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	18.786us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	47.029us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	729.912us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	103.165us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	37.546us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	47.029us	20	20	100.00
		pattgen_csr_aliasing	3.000s	103.165us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.050m	2.769ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.617m	9.877ms	50	50	100.00
V2	error	pattgen_error	8.000s	58.353us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.850m	4.007ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	136.358us	50	50	100.00
V2	intr_test	pattgen_intr_test	8.000s	26.924us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	37.985us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	37.985us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	18.786us	5	5	100.00
		pattgen_csr_rw	3.000s	47.029us	20	20	100.00
		pattgen_csr_aliasing	3.000s	103.165us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	19.592us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	18.786us	5	5	100.00
		pattgen_csr_rw	3.000s	47.029us	20	20	100.00
		pattgen_csr_aliasing	3.000s	103.165us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	19.592us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	43.208us	20	20	100.00
		pattgen_sec_cm	2.000s	33.667us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	43.208us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	25.650m	312.987ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			486	520	93.46

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 34 failures:

Test pattgen_stress_all_with_rand_reset has 34 failures.

0.pattgen_stress_all_with_rand_reset.57956687158688470794494152201695985363055017968547440703248517032200591823364
Line 333, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 353918898 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 353920140 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 353920140 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/5
  UVM_INFO @ 354022180 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.12353328287624853895388623832723180175947477344616603518992756125222060637024
Line 576, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 14734932458 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 14734935466 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 14734935466 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/5
  UVM_INFO @ 14734996072 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 32 more failures.