PATTGEN Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: `1fbe1ece8d`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	163.414us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	31.789us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	7.000s	30.569us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	232.342us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	32.424us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	12.000s	36.586us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	7.000s	30.569us	20	20	100.00
		pattgen_csr_aliasing	3.000s	32.424us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.967m	11.543ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.867m	5.374ms	50	50	100.00
V2	error	pattgen_error	6.000s	16.685us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.700m	5.550ms	50	50	100.00
V2	alert_test	pattgen_alert_test	8.000s	21.445us	50	50	100.00
V2	intr_test	pattgen_intr_test	12.000s	39.733us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	9.000s	134.589us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	9.000s	134.589us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	31.789us	5	5	100.00
		pattgen_csr_rw	7.000s	30.569us	20	20	100.00
		pattgen_csr_aliasing	3.000s	32.424us	5	5	100.00
		pattgen_same_csr_outstanding	8.000s	20.577us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	31.789us	5	5	100.00
		pattgen_csr_rw	7.000s	30.569us	20	20	100.00
		pattgen_csr_aliasing	3.000s	32.424us	5	5	100.00
		pattgen_same_csr_outstanding	8.000s	20.577us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	7.000s	210.283us	20	20	100.00
		pattgen_sec_cm	3.000s	496.845us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	7.000s	210.283us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	28.900m	408.641ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			483	520	92.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 33 failures:

Test pattgen_stress_all_with_rand_reset has 33 failures.

0.pattgen_stress_all_with_rand_reset.30855649925296095710307837654134103535170810822140823638292699492678452919444
Line 306, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 762157288 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 762164348 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 762164348 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/10
  UVM_INFO @ 762206015 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.11462500867840987098055321800790822745801549238658013393317752888638481553653
Line 534, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 48576251658 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 48576285883 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 48576285883 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 3/5
  UVM_INFO @ 48576422248 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 31 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 4 failures:
- Test pattgen_stress_all_with_rand_reset has 4 failures.
  - 3.pattgen_stress_all_with_rand_reset.106273856089922862907544349034536922545888723730560919005948674572715790424117
    Line 298, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 161640108 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 16.pattgen_stress_all_with_rand_reset.36242298192405910369787896081289961824903606315011867216738088905082239505121
    Line 373, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/16.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3144638264 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 2 more failures.