PATTGEN Simulation Results

Sunday April 07 2024 19:02:41 UTC

GitHub Revision: `7773b039d0`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 110372901762865644007400082009110088154180821215015477169464044145224727696933

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	8.000s	33.983us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	48.750us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	33.213us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	482.384us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	264.211us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	29.806us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	33.213us	20	20	100.00
		pattgen_csr_aliasing	3.000s	264.211us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.867m	2.637ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.800m	10.961ms	50	50	100.00
V2	error	pattgen_error	8.000s	36.029us	50	50	100.00
V2	stress_all	pattgen_stress_all	4.633m	13.409ms	50	50	100.00
V2	alert_test	pattgen_alert_test	8.000s	14.309us	50	50	100.00
V2	intr_test	pattgen_intr_test	8.000s	14.794us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	461.725us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	461.725us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	48.750us	5	5	100.00
		pattgen_csr_rw	4.000s	33.213us	20	20	100.00
		pattgen_csr_aliasing	3.000s	264.211us	5	5	100.00
		pattgen_same_csr_outstanding	8.000s	16.646us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	48.750us	5	5	100.00
		pattgen_csr_rw	4.000s	33.213us	20	20	100.00
		pattgen_csr_aliasing	3.000s	264.211us	5	5	100.00
		pattgen_same_csr_outstanding	8.000s	16.646us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	91.477us	20	20	100.00
		pattgen_sec_cm	3.000s	114.747us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	91.477us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	22.817m	111.427ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			485	520	93.27

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 28 failures:

Test pattgen_stress_all_with_rand_reset has 28 failures.

2.pattgen_stress_all_with_rand_reset.63868096807230068076430724863960853696179755076649745896043905253628531161939
Line 446, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8857518970 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 8857526320 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 8857526320 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/5
  UVM_INFO @ 8857586320 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

3.pattgen_stress_all_with_rand_reset.44486674242013887463937973043681092857339294084136565075980259928050790821314
Line 290, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 432615191 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 432620182 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 432620182 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @ 432900182 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 26 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 7 failures:
- Test pattgen_stress_all_with_rand_reset has 7 failures.
  - 1.pattgen_stress_all_with_rand_reset.71669432386708738953815875861838939963262550597953318630505186229126246550171
    Line 541, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 17704685634 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 8.pattgen_stress_all_with_rand_reset.48193689353941033441969872032244806439757670429130113795076027487874771830147
    Line 1018, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/8.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 45323702573 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - ... and 5 more failures.