PATTGEN Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: `4fd94db59a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	14.000s	357.683us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	65.888us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	6.000s	14.404us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	1.597ms	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	129.849us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	7.000s	59.884us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	6.000s	14.404us	20	20	100.00
		pattgen_csr_aliasing	3.000s	129.849us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.117m	11.452ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.967m	2.636ms	50	50	100.00
V2	error	pattgen_error	9.000s	19.262us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.033m	4.352ms	50	50	100.00
V2	alert_test	pattgen_alert_test	8.000s	28.573us	50	50	100.00
V2	intr_test	pattgen_intr_test	4.000s	11.761us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	111.415us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	111.415us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	65.888us	5	5	100.00
		pattgen_csr_rw	6.000s	14.404us	20	20	100.00
		pattgen_csr_aliasing	3.000s	129.849us	5	5	100.00
		pattgen_same_csr_outstanding	12.000s	53.349us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	65.888us	5	5	100.00
		pattgen_csr_rw	6.000s	14.404us	20	20	100.00
		pattgen_csr_aliasing	3.000s	129.849us	5	5	100.00
		pattgen_same_csr_outstanding	12.000s	53.349us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	7.000s	259.893us	20	20	100.00
		pattgen_sec_cm	7.000s	243.956us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	7.000s	259.893us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	44.867m	101.547ms	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			483	520	92.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 30 failures:

Test pattgen_stress_all_with_rand_reset has 30 failures.

0.pattgen_stress_all_with_rand_reset.24043162604930118356399140449979003775041905173744113952151776638198566032864
Line 380, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9023878839 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 9023887729 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 9023887729 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/10
  UVM_INFO @ 9023931847 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.76993446944458644795497932056330100866657674948072388643770332450130121110974
Line 826, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 29895657937 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 29895663652 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 29895663652 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 4/5
  UVM_INFO @ 29895744460 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 28 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 7 failures:
- Test pattgen_stress_all_with_rand_reset has 7 failures.
  - 14.pattgen_stress_all_with_rand_reset.84865878075768689054390953553537095489910630317321615904157527701202148858286
    Line 407, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/14.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 16104019197 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - 22.pattgen_stress_all_with_rand_reset.39369644740980813207927120193083813710869246251011610857282309207567169225791
    Line 415, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/22.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 29440212671 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 5 more failures.