PATTGEN Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: `41bc3e0c7f`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	323.362us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	17.622us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	10.679us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	8.000s	67.934us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	30.786us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	185.713us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	10.679us	20	20	100.00
		pattgen_csr_aliasing	3.000s	30.786us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.883m	2.774ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.850m	50.941ms	50	50	100.00
V2	error	pattgen_error	4.000s	58.462us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.767m	16.198ms	50	50	100.00
V2	alert_test	pattgen_alert_test	4.000s	69.882us	50	50	100.00
V2	intr_test	pattgen_intr_test	4.000s	37.478us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	277.153us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	277.153us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	17.622us	5	5	100.00
		pattgen_csr_rw	3.000s	10.679us	20	20	100.00
		pattgen_csr_aliasing	3.000s	30.786us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	109.757us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	17.622us	5	5	100.00
		pattgen_csr_rw	3.000s	10.679us	20	20	100.00
		pattgen_csr_aliasing	3.000s	30.786us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	109.757us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	145.843us	20	20	100.00
		pattgen_sec_cm	3.000s	167.715us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	145.843us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	40.950m	119.197ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			484	520	93.08

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 33 failures:

Test pattgen_stress_all_with_rand_reset has 33 failures.

2.pattgen_stress_all_with_rand_reset.59073423661518985726057136989463139635308622915601722142323322013632554594244
Line 384, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4880038408 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 4880044787 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4880044787 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 2/5
  UVM_INFO @ 4880096872 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

3.pattgen_stress_all_with_rand_reset.40594529805048961110810582998437510957151992313182295552244078862435341459357
Line 949, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 71436508808 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 71436514260 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 71436514260 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 7/10
  UVM_INFO @ 71436561135 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 31 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 3 failures:
- Test pattgen_stress_all_with_rand_reset has 3 failures.
  - 13.pattgen_stress_all_with_rand_reset.75007430306727202076654091987601209737450470268170180768031453609262969847220
    Line 316, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/13.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 853879691 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 39.pattgen_stress_all_with_rand_reset.110576729624392740565733170814755171296805298625276378301131474813734936902325
    Line 492, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/39.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 12286790716 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 1 more failures.