PATTGEN Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: `b938dde05c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	8.000s	321.436us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	48.231us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	12.000s	15.540us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	848.807us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	77.654us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	7.000s	63.813us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	12.000s	15.540us	20	20	100.00
		pattgen_csr_aliasing	4.000s	77.654us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.733m	3.988ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.783m	7.743ms	50	50	100.00
V2	error	pattgen_error	5.000s	43.344us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.450m	5.459ms	50	50	100.00
V2	alert_test	pattgen_alert_test	7.000s	71.545us	50	50	100.00
V2	intr_test	pattgen_intr_test	7.000s	25.630us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	12.000s	49.095us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	12.000s	49.095us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	48.231us	5	5	100.00
		pattgen_csr_rw	12.000s	15.540us	20	20	100.00
		pattgen_csr_aliasing	4.000s	77.654us	5	5	100.00
		pattgen_same_csr_outstanding	11.000s	27.255us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	48.231us	5	5	100.00
		pattgen_csr_rw	12.000s	15.540us	20	20	100.00
		pattgen_csr_aliasing	4.000s	77.654us	5	5	100.00
		pattgen_same_csr_outstanding	11.000s	27.255us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	8.000s	247.876us	20	20	100.00
		pattgen_sec_cm	3.000s	118.574us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	8.000s	247.876us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	52.150m	145.895ms	10	50	20.00
V3		TOTAL			10	50	20.00
		TOTAL			480	520	92.31

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 36 failures:

Test pattgen_stress_all_with_rand_reset has 36 failures.

0.pattgen_stress_all_with_rand_reset.114811703210373943803416117706785483620538458375010807229568429808592440658938
Line 330, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1985137769 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1985145099 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1985145099 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @ 1985176350 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.78856530869827378538326790110851322462878346539561528943321120252057828084008
Line 297, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1093779281 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1093784820 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1093784820 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @ 1093864820 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 34 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 4 failures:
- Test pattgen_stress_all_with_rand_reset has 4 failures.
  - 13.pattgen_stress_all_with_rand_reset.6678803567459577575120076387598642356503148454112509763689223410831750435556
    Line 312, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/13.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 497705327 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 15.pattgen_stress_all_with_rand_reset.90892912870913274260183514939972519647652253636106951611808630606155252683931
    Line 822, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/15.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 386267148038 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - ... and 2 more failures.