PATTGEN Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: `ae68723071`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	17.000s	2.514ms	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	38.558us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	13.713us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	281.919us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	18.398us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	83.916us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	13.713us	20	20	100.00
		pattgen_csr_aliasing	3.000s	18.398us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.917m	5.489ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.850m	2.634ms	50	50	100.00
V2	error	pattgen_error	12.000s	39.575us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.767m	16.524ms	50	50	100.00
V2	alert_test	pattgen_alert_test	8.000s	13.996us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	14.045us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	169.693us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	169.693us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	38.558us	5	5	100.00
		pattgen_csr_rw	3.000s	13.713us	20	20	100.00
		pattgen_csr_aliasing	3.000s	18.398us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	29.398us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	38.558us	5	5	100.00
		pattgen_csr_rw	3.000s	13.713us	20	20	100.00
		pattgen_csr_aliasing	3.000s	18.398us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	29.398us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	49.986us	20	20	100.00
		pattgen_sec_cm	7.000s	64.323us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	49.986us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	37.900m	397.111ms	12	50	24.00
V3		TOTAL			12	50	24.00
		TOTAL			482	520	92.69

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 32 failures:

Test pattgen_stress_all_with_rand_reset has 32 failures.

0.pattgen_stress_all_with_rand_reset.108669014975655651247330037747895759179692014023970984971109862791698551317392
Line 1257, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 200327018040 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 200327055393 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 200327055393 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 8/10
  UVM_INFO @ 200327229305 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.74337696151771643207343264317059425500264288469610561406658442170833476306835
Line 355, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 25867641394 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 25867645625 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 25867645625 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @ 25867931339 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 30 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 6 failures:
- Test pattgen_stress_all_with_rand_reset has 6 failures.
  - 17.pattgen_stress_all_with_rand_reset.728068429540193119636441034077041535075124086126368197830749877051892203694
    Line 813, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/17.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 140069603832 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - 36.pattgen_stress_all_with_rand_reset.11296877134775985295964756408285593677454111823604926065622262070793611392906
    Line 311, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/36.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 250984572 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 4 more failures.