PATTGEN Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: `0cb61fc7e7`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	8.000s	163.486us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	34.125us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	17.059us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	252.883us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	27.457us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	8.000s	29.286us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	17.059us	20	20	100.00
		pattgen_csr_aliasing	3.000s	27.457us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.850m	3.988ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.967m	2.745ms	50	50	100.00
V2	error	pattgen_error	7.000s	25.591us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.117m	25.004ms	50	50	100.00
V2	alert_test	pattgen_alert_test	7.000s	33.233us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	13.680us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	47.972us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	47.972us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	34.125us	5	5	100.00
		pattgen_csr_rw	3.000s	17.059us	20	20	100.00
		pattgen_csr_aliasing	3.000s	27.457us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	69.341us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	34.125us	5	5	100.00
		pattgen_csr_rw	3.000s	17.059us	20	20	100.00
		pattgen_csr_aliasing	3.000s	27.457us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	69.341us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	831.888us	20	20	100.00
		pattgen_sec_cm	2.000s	65.496us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	831.888us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	30.183m	80.619ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			488	520	93.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	100.00	100.00	100.00	99.06	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:830) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 28 failures:

Test pattgen_stress_all_with_rand_reset has 28 failures.

0.pattgen_stress_all_with_rand_reset.115393454183464711591927083061358132748224174212272009730479279088325953187161
Line 1281, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 337794316088 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 337794356555 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 337794356555 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 7/10
  UVM_INFO @ 337794606557 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

4.pattgen_stress_all_with_rand_reset.45836390204494979858696007065919851311094856223726934666554098686733266325956
Line 328, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1590546092 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1590549252 ps: (cip_base_vseq.sv:754) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1590549252 ps: (cip_base_vseq.sv:757) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Reset is issued for run 1/5
  UVM_INFO @ 1590580503 ps: (cip_base_vseq.sv:765) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 26 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 4 failures:
- Test pattgen_stress_all_with_rand_reset has 4 failures.
  - 3.pattgen_stress_all_with_rand_reset.74144645949075045630974361911626011118885978973302621114278927144222520954277
    Line 621, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19046621794 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 20.pattgen_stress_all_with_rand_reset.531606601298330200831248988577227256048461864775016767283065385228172439095
    Line 307, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/20.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 197927983 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 2 more failures.