PATTGEN Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: `29d22a60a2`

Branch: os_regression_2024_10_08

Simulator: XCELIUM

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	48.000s	137.789us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	31.895us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	1.317m	16.638us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	6.000s	1.043ms	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	50.487us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	1.333m	35.496us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.317m	16.638us	20	20	100.00
		pattgen_csr_aliasing	4.000s	50.487us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.650m	8.224ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.867m	10.518ms	50	50	100.00
V2	error	pattgen_error	49.000s	226.973us	50	50	100.00
V2	stress_all	pattgen_stress_all	5.267m	73.969ms	50	50	100.00
V2	alert_test	pattgen_alert_test	45.000s	11.676us	50	50	100.00
V2	intr_test	pattgen_intr_test	1.350m	26.812us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	1.300m	508.439us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	1.300m	508.439us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	31.895us	5	5	100.00
		pattgen_csr_rw	1.317m	16.638us	20	20	100.00
		pattgen_csr_aliasing	4.000s	50.487us	5	5	100.00
		pattgen_same_csr_outstanding	1.333m	28.448us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	31.895us	5	5	100.00
		pattgen_csr_rw	1.317m	16.638us	20	20	100.00
		pattgen_csr_aliasing	4.000s	50.487us	5	5	100.00
		pattgen_same_csr_outstanding	1.333m	28.448us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	1.217m	535.104us	20	20	100.00
		pattgen_sec_cm	4.000s	120.230us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	1.217m	535.104us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	3.183m	5.221ms	5	50	10.00
V3		TOTAL			5	50	10.00
	Unmapped tests	pattgen_inactive_level	2.633m	10.004ms	45	50	90.00
		TOTAL			520	570	91.23

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 44 failures:

Test pattgen_stress_all_with_rand_reset has 44 failures.

0.pattgen_stress_all_with_rand_reset.47172640738493912675306593358102867631124894481277744178376437258109480597769
Line 132, in log /workspaces/repo/scratch/os_regression_2024_10_08/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1160946112 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1160956380 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1160956380 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/10
  UVM_INFO @ 1161248049 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.4321364083935481322338656409003749300270525240284641241390599918799365685510
Line 149, in log /workspaces/repo/scratch/os_regression_2024_10_08/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 229562910 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 229565855 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 229565855 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/5
  UVM_INFO @ 229645855 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 42 more failures.

UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 5.pattgen_inactive_level.96563780304412349683872862341568029907236134362522679467751798357922250074332
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_10_08/pattgen-sim-xcelium/5.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10003727106 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x87f41d10, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10003727106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 14.pattgen_inactive_level.11233037898386695316133574023548498357631466441901514826274970977651728914135
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_10_08/pattgen-sim-xcelium/14.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10031142881 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x88661d50, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
  UVM_INFO @ 10031142881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=26) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 32.pattgen_inactive_level.109872636532846836351086699934363308428531148130982313272713440979129773092919
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_10_08/pattgen-sim-xcelium/32.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10158828911 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xa3088510, Comparison=CompareOpEq, exp_data=0x0, call_count=26)
  UVM_INFO @ 10158828911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 1 failures:
- Test pattgen_stress_all_with_rand_reset has 1 failures.
  - 35.pattgen_stress_all_with_rand_reset.107700508069103177812876994594040602735979710990825864822882399608311027039707
    Line 116, in log /workspaces/repo/scratch/os_regression_2024_10_08/pattgen-sim-xcelium/35.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  69252627 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 40.pattgen_inactive_level.46804762085559860477255554586591333513110191153536731008137545516811340202706
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_10_08/pattgen-sim-xcelium/40.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10068480863 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x737ab990, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10068480863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=27) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 49.pattgen_inactive_level.62253105444809331941635958737456104495565588706877238804944924436314177529513
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_10_08/pattgen-sim-xcelium/49.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10097572046 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xab4afc10, Comparison=CompareOpEq, exp_data=0x0, call_count=27)
  UVM_INFO @ 10097572046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```