PATTGEN Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: `1cb1c3d135`

Branch: os_regression_2024_10_02

Simulator: XCELIUM

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	15.000s	427.684us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	20.242us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	19.037us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	6.000s	409.156us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	48.187us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	34.073us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	19.037us	20	20	100.00
		pattgen_csr_aliasing	3.000s	48.187us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.350m	2.711ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	2.017m	5.162ms	50	50	100.00
V2	error	pattgen_error	14.000s	47.383us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.017m	4.133ms	50	50	100.00
V2	alert_test	pattgen_alert_test	10.000s	27.404us	50	50	100.00
V2	intr_test	pattgen_intr_test	14.000s	26.958us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	354.288us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	354.288us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	20.242us	5	5	100.00
		pattgen_csr_rw	4.000s	19.037us	20	20	100.00
		pattgen_csr_aliasing	3.000s	48.187us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	27.985us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	20.242us	5	5	100.00
		pattgen_csr_rw	4.000s	19.037us	20	20	100.00
		pattgen_csr_aliasing	3.000s	48.187us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	27.985us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	5.000s	307.525us	20	20	100.00
		pattgen_sec_cm	13.000s	64.397us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	5.000s	307.525us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	3.900m	18.697ms	0	50	0.00
V3		TOTAL			0	50	0.00
	Unmapped tests	pattgen_inactive_level	5.583m	10.030ms	47	50	94.00
		TOTAL			517	570	90.70

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 39 failures:

Test pattgen_stress_all_with_rand_reset has 39 failures.

0.pattgen_stress_all_with_rand_reset.25812165393843117579353926302637570736191994760575953858596275847148562447681
Line 122, in log /workspaces/repo/scratch/os_regression_2024_10_02/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 490611555 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 490622021 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 490622021 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 490795933 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.104630114419602185045563354717438570257684173345461638701818800907359962180523
Line 182, in log /workspaces/repo/scratch/os_regression_2024_10_02/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 525806003 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 525810056 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 525810056 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/10
  UVM_INFO @ 525911066 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 37 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 9 failures:

Test pattgen_stress_all_with_rand_reset has 9 failures.

3.pattgen_stress_all_with_rand_reset.2450242771991127139013296618653829111524404099550310120699265625230685748008
Line 140, in log /workspaces/repo/scratch/os_regression_2024_10_02/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 290132447 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_pattgen_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_pattgen_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_ERROR @ 290132447 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_pattgen_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_pattgen_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 290243559 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Stress w/ reset is done for run 2/5
  UVM_INFO @ 294955335 ps: (cip_base_vseq.sv:727) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] running run_seq_with_rand_reset_vseq iteration 3/5

6.pattgen_stress_all_with_rand_reset.49186103523833405799348890898646045546541122259810698100159060666893779698061
Line 117, in log /workspaces/repo/scratch/os_regression_2024_10_02/pattgen-sim-xcelium/6.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  47980513 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_pattgen_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_pattgen_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_ERROR @  47980513 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_pattgen_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_pattgen_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  48040513 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Stress w/ reset is done for run 1/10
  UVM_INFO @  48682468 ps: (cip_base_vseq.sv:727) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] running run_seq_with_rand_reset_vseq iteration 2/10

... and 7 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 21.pattgen_stress_all_with_rand_reset.101144363973176944251416162759918568935231974350027599440677884608707428374317
    Line 202, in log /workspaces/repo/scratch/os_regression_2024_10_02/pattgen-sim-xcelium/21.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3227640401 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 47.pattgen_stress_all_with_rand_reset.113274441789756430539800414883268431573760269357139056720496274335682662732421
    Line 266, in log /workspaces/repo/scratch/os_regression_2024_10_02/pattgen-sim-xcelium/47.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1573766784 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
UVM_FATAL (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 5.pattgen_inactive_level.27457870164919619550447059041120847531982471925535027503801036804656691710464
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_10_02/pattgen-sim-xcelium/5.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10029255338 ps: (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc8bae0d0, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10029255338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 21.pattgen_inactive_level.5648737605098311451520024771453520284205388814241404494619932898350534162209
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_10_02/pattgen-sim-xcelium/21.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10030087342 ps: (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x3cf3590, Comparison=CompareOpEq, exp_data=0x0, call_count=18)
  UVM_INFO @ 10030087342 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 28.pattgen_inactive_level.45163777786078509161255635727250353277795578597490083385734648229571355699065
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_10_02/pattgen-sim-xcelium/28.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10030394919 ps: (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x38e9e450, Comparison=CompareOpEq, exp_data=0x0, call_count=23)
  UVM_INFO @ 10030394919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```