PATTGEN Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: `78ad89d1aa`

Branch: os_regression_2024_09_23

Simulator: XCELIUM

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	42.000s	32.260us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	35.713us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	1.050m	51.434us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	6.000s	295.682us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	41.516us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	1.750m	40.878us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.050m	51.434us	20	20	100.00
		pattgen_csr_aliasing	3.000s	41.516us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.900m	2.639ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.950m	5.344ms	50	50	100.00
V2	error	pattgen_error	43.000s	34.748us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.833m	20.957ms	50	50	100.00
V2	alert_test	pattgen_alert_test	30.000s	29.124us	50	50	100.00
V2	intr_test	pattgen_intr_test	1.800m	16.025us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.167m	48.468us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.167m	48.468us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	35.713us	5	5	100.00
		pattgen_csr_rw	1.050m	51.434us	20	20	100.00
		pattgen_csr_aliasing	3.000s	41.516us	5	5	100.00
		pattgen_same_csr_outstanding	1.367m	21.646us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	35.713us	5	5	100.00
		pattgen_csr_rw	1.050m	51.434us	20	20	100.00
		pattgen_csr_aliasing	3.000s	41.516us	5	5	100.00
		pattgen_same_csr_outstanding	1.367m	21.646us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	1.750m	305.930us	20	20	100.00
		pattgen_sec_cm	18.000s	200.004us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	1.750m	305.930us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	4.217m	26.640ms	1	50	2.00
V3		TOTAL			1	50	2.00
	Unmapped tests	pattgen_inactive_level	45.000s	10.018ms	48	50	96.00
		TOTAL			519	570	91.05

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:

Test pattgen_stress_all_with_rand_reset has 34 failures.

0.pattgen_stress_all_with_rand_reset.74292187242427993072700811413032725489159224000500993760618403937268006380377
Line 106, in log /workspaces/repo/scratch/os_regression_2024_09_23/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 472592857 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 472600811 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 472600811 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 472704981 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

3.pattgen_stress_all_with_rand_reset.20228168727085918200664571508656586545677546626212366770503922302184143245819
Line 114, in log /workspaces/repo/scratch/os_regression_2024_09_23/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4738206688 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 4738218077 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4738218077 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 4738652857 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 32 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 15 failures:

Test pattgen_stress_all_with_rand_reset has 15 failures.

1.pattgen_stress_all_with_rand_reset.52878541378649331341044821760366528762948442943367682439908290519658574090368
Line 117, in log /workspaces/repo/scratch/os_regression_2024_09_23/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 203898076 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_pattgen_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_pattgen_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_ERROR @ 203898076 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_pattgen_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_pattgen_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 204231412 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Stress w/ reset is done for run 1/10
  UVM_INFO @ 210063522 ps: (cip_base_vseq.sv:727) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] running run_seq_with_rand_reset_vseq iteration 2/10

2.pattgen_stress_all_with_rand_reset.31318712213563712753887870400498341095416285342806968803696408352739523850327
Line 152, in log /workspaces/repo/scratch/os_regression_2024_09_23/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2556711327 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_pattgen_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_pattgen_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_ERROR @ 2556711327 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_pattgen_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_pattgen_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2556794661 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Stress w/ reset is done for run 2/10
  UVM_INFO @ 2560129711 ps: (cip_base_vseq.sv:727) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] running run_seq_with_rand_reset_vseq iteration 3/10

... and 13 more failures.

UVM_FATAL (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 28.pattgen_inactive_level.47154536702714203328138550875930782177984197505512729183859141831710985782160
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_23/pattgen-sim-xcelium/28.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10017847297 ps: (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x5020f910, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10017847297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 42.pattgen_inactive_level.53639788478247697476594459392533531947248791414595431730770548011313018827923
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_23/pattgen-sim-xcelium/42.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10094884447 ps: (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x6dbb7810, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
  UVM_INFO @ 10094884447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```