PATTGEN Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: `7e34e67ade`

Branch: os_regression_2024_09_17

Simulator: XCELIUM

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	1.767m	149.879us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	13.697us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	40.826us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	63.922us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	57.500us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	19.829us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	40.826us	20	20	100.00
		pattgen_csr_aliasing	3.000s	57.500us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	3.350m	5.529ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	2.567m	5.501ms	50	50	100.00
V2	error	pattgen_error	1.550m	26.943us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.167m	2.725ms	50	50	100.00
V2	alert_test	pattgen_alert_test	1.500m	39.075us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	36.304us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	35.068us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	35.068us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	13.697us	5	5	100.00
		pattgen_csr_rw	3.000s	40.826us	20	20	100.00
		pattgen_csr_aliasing	3.000s	57.500us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	83.048us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	13.697us	5	5	100.00
		pattgen_csr_rw	3.000s	40.826us	20	20	100.00
		pattgen_csr_aliasing	3.000s	57.500us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	83.048us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	203.718us	20	20	100.00
		pattgen_sec_cm	3.000s	1.011ms	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	203.718us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	4.117m	101.797ms	4	50	8.00
V3		TOTAL			4	50	8.00
	Unmapped tests	pattgen_inactive_level	1.733m	89.762us	48	50	96.00
		TOTAL			522	570	91.58

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 43 failures:

Test pattgen_stress_all_with_rand_reset has 43 failures.

0.pattgen_stress_all_with_rand_reset.64677233788451312743694244166924038125855263431383563262833571152246044122757
Line 142, in log /workspaces/repo/scratch/os_regression_2024_09_17/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 729057627 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 729062504 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 729062504 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/5
  UVM_INFO @ 729135674 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.4478021267283842449519872170720938041930467230423908925444374693416589976183
Line 121, in log /workspaces/repo/scratch/os_regression_2024_09_17/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 747990983 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 747994456 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 747994456 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 748056958 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 41 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 3 failures:
- Test pattgen_stress_all_with_rand_reset has 3 failures.
  - 9.pattgen_stress_all_with_rand_reset.107515865130346212181434105768809433263340698422784044649107648132692242968657
    Line 111, in log /workspaces/repo/scratch/os_regression_2024_09_17/pattgen-sim-xcelium/9.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1111816916 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - 13.pattgen_stress_all_with_rand_reset.80075501368578719159187240757751859488773951578640038041904224226557073083747
    Line 119, in log /workspaces/repo/scratch/os_regression_2024_09_17/pattgen-sim-xcelium/13.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 118507962 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 4.pattgen_inactive_level.19994905167829453168223538963158463171645427607639286962777462636081258310071
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_17/pattgen-sim-xcelium/4.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10024617049 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x6462bc50, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
  UVM_INFO @ 10024617049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 19.pattgen_inactive_level.114959283750494874857439279742858874124234676497593722696644652445944088482241
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_17/pattgen-sim-xcelium/19.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10041793017 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x99f56dd0, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10041793017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```