PATTGEN Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: `8a1401d614`

Branch: os_regression_2024_10_11

Simulator: XCELIUM

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	11.000s	1.035ms	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	71.276us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	38.130us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	6.000s	1.044ms	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	38.488us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	20.903us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	38.130us	20	20	100.00
		pattgen_csr_aliasing	3.000s	38.488us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.467m	5.378ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	2.383m	10.955ms	50	50	100.00
V2	error	pattgen_error	4.000s	179.458us	50	50	100.00
V2	stress_all	pattgen_stress_all	4.717m	27.600ms	50	50	100.00
V2	alert_test	pattgen_alert_test	4.000s	41.359us	50	50	100.00
V2	intr_test	pattgen_intr_test	4.000s	23.659us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	436.301us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	436.301us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	71.276us	5	5	100.00
		pattgen_csr_rw	4.000s	38.130us	20	20	100.00
		pattgen_csr_aliasing	3.000s	38.488us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	26.013us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	71.276us	5	5	100.00
		pattgen_csr_rw	4.000s	38.130us	20	20	100.00
		pattgen_csr_aliasing	3.000s	38.488us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	26.013us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	5.000s	44.210us	20	20	100.00
		pattgen_sec_cm	4.000s	58.376us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	5.000s	44.210us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	5.850m	24.845ms	1	50	2.00
V3		TOTAL			1	50	2.00
	Unmapped tests	pattgen_inactive_level	51.000s	10.328ms	47	50	94.00
		TOTAL			518	570	90.88

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 48 failures:

Test pattgen_stress_all_with_rand_reset has 48 failures.

0.pattgen_stress_all_with_rand_reset.49553169259612641851705481244457273520267860100445499995885923891898616497044
Line 343, in log /workspaces/repo/scratch/os_regression_2024_10_11/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11947277810 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 11947309799 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 11947309799 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 5/5
  UVM_INFO @ 11947386723 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.47722269096338499394954864860471622848855008961443264088205484598450315435471
Line 161, in log /workspaces/repo/scratch/os_regression_2024_10_11/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2058753354 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 2058761332 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2058761332 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/10
  UVM_INFO @ 2058947380 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 46 more failures.

UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 8.pattgen_inactive_level.93033242395122974130192842825710003879294166455439292721740087146982927099597
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_10_11/pattgen-sim-xcelium/8.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10009569985 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x98216a90, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10009569985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 1 failures:
- Test pattgen_stress_all_with_rand_reset has 1 failures.
  - 14.pattgen_stress_all_with_rand_reset.98637933308209614534078501470539679114072857748284924803441894328414862025560
    Line 415, in log /workspaces/repo/scratch/os_regression_2024_10_11/pattgen-sim-xcelium/14.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2900020330 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 18.pattgen_inactive_level.63799816775220837820957474850457413511507832425694870102589539313129043959221
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_10_11/pattgen-sim-xcelium/18.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10161295324 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x5f40e250, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
  UVM_INFO @ 10161295324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 46.pattgen_inactive_level.38139344498042644871606329722671006834213724357470243328875724311377471372222
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_10_11/pattgen-sim-xcelium/46.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10328356404 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x78c88790, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10328356404 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```