PWM Simulation Results

Thursday May 25 2023 07:02:34 UTC

GitHub Revision: `94eb0df12`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 77475240

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	6.000s	527.915us	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	21.721us	5	5	100.00
V1	csr_rw	pwm_csr_rw	4.000s	44.507us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	12.000s	1.880ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	5.000s	35.354us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	4.000s	24.832us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	4.000s	44.507us	20	20	100.00
		pwm_csr_aliasing	5.000s	35.354us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	53.000s	10.941ms	50	50	100.00
V2	pulse	pwm_rand_output	53.000s	10.941ms	50	50	100.00
V2	blink	pwm_rand_output	53.000s	10.941ms	50	50	100.00
V2	heartbeat	pwm_rand_output	53.000s	10.941ms	50	50	100.00
V2	resolution	pwm_rand_output	53.000s	10.941ms	50	50	100.00
V2	multi_channel	pwm_rand_output	53.000s	10.941ms	50	50	100.00
V2	polarity	pwm_rand_output	53.000s	10.941ms	50	50	100.00
V2	phase	pwm_rand_output	53.000s	10.941ms	50	50	100.00
V2	lowpower	pwm_rand_output	53.000s	10.941ms	50	50	100.00
V2	perf	pwm_perf	51.000s	10.506ms	50	50	100.00
V2	stress_all	pwm_stress_all	4.567m	262.517ms	47	50	94.00
V2	alert_test	pwm_alert_test	5.000s	15.411us	50	50	100.00
V2	intr_test	pwm_intr_test	3.000s	16.300us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	8.000s	205.076us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	8.000s	205.076us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	21.721us	5	5	100.00
		pwm_csr_rw	4.000s	44.507us	20	20	100.00
		pwm_csr_aliasing	5.000s	35.354us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	53.135us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	21.721us	5	5	100.00
		pwm_csr_rw	4.000s	44.507us	20	20	100.00
		pwm_csr_aliasing	5.000s	35.354us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	53.135us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	pwm_tl_intg_err	7.000s	284.673us	20	20	100.00
		pwm_sec_cm	3.000s	242.978us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	7.000s	284.673us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			417	420	99.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.26	99.26	98.64	99.84	94.38	94.92	--	100.00	99.34

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 3 failures:

Test pwm_stress_all has 3 failures.

6.pwm_stress_all.2782578385
Line 2693, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/6.pwm_stress_all/latest/run.log

  UVM_ERROR @ 45773359208 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 45773359208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.pwm_stress_all.657536704
Line 3357872, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/9.pwm_stress_all/latest/run.log

  UVM_ERROR @ 94655882857 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 94655882857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.