PWM Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: `213e792ea`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 2340441291

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	6.000s	4.227ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	52.169us	5	5	100.00
V1	csr_rw	pwm_csr_rw	4.000s	78.994us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	11.000s	595.291us	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	5.000s	290.405us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	5.000s	201.002us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	4.000s	78.994us	20	20	100.00
		pwm_csr_aliasing	5.000s	290.405us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.700m	43.746ms	50	50	100.00
V2	pulse	pwm_rand_output	1.700m	43.746ms	50	50	100.00
V2	blink	pwm_rand_output	1.700m	43.746ms	50	50	100.00
V2	heartbeat	pwm_rand_output	1.700m	43.746ms	50	50	100.00
V2	resolution	pwm_rand_output	1.700m	43.746ms	50	50	100.00
V2	multi_channel	pwm_rand_output	1.700m	43.746ms	50	50	100.00
V2	polarity	pwm_rand_output	1.700m	43.746ms	50	50	100.00
V2	phase	pwm_rand_output	1.700m	43.746ms	50	50	100.00
V2	lowpower	pwm_rand_output	1.700m	43.746ms	50	50	100.00
V2	perf	pwm_perf	52.000s	43.755ms	50	50	100.00
V2	stress_all	pwm_stress_all	7.200m	717.045ms	46	50	92.00
V2	alert_test	pwm_alert_test	4.000s	23.517us	50	50	100.00
V2	intr_test	pwm_intr_test	5.000s	36.658us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	6.000s	325.285us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	6.000s	325.285us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	52.169us	5	5	100.00
		pwm_csr_rw	4.000s	78.994us	20	20	100.00
		pwm_csr_aliasing	5.000s	290.405us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	353.862us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	52.169us	5	5	100.00
		pwm_csr_rw	4.000s	78.994us	20	20	100.00
		pwm_csr_aliasing	5.000s	290.405us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	353.862us	20	20	100.00
V2		TOTAL			286	290	98.62
V2S	tl_intg_err	pwm_tl_intg_err	7.000s	526.899us	20	20	100.00
		pwm_sec_cm	4.000s	37.236us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	7.000s	526.899us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			416	420	99.05

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.76	99.76	99.57	100.00	95.41	94.92	--	100.00	99.34

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 4 failures:

Test pwm_stress_all has 4 failures.

26.pwm_stress_all.2704472056
Line 1574384, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/26.pwm_stress_all/latest/run.log

  UVM_ERROR @ 11918419474 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 11918419474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.pwm_stress_all.152778082
Line 247759, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/38.pwm_stress_all/latest/run.log

  UVM_ERROR @ 84296598474 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [4] did not MATCH
  UVM_INFO @ 84296598474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.