PWM Simulation Results

Wednesday January 03 2024 20:02:50 UTC

GitHub Revision: 748235cbb6

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 25438953283828179064589190240910206115356752103516363191807863392753441298838

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 14.000s 547.955us 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 7.000s 69.795us 5 5 100.00
V1 csr_rw pwm_csr_rw 7.000s 31.936us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 11.000s 322.898us 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 5.000s 104.565us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 12.000s 31.125us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 7.000s 31.936us 20 20 100.00
pwm_csr_aliasing 5.000s 104.565us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.583m 21.875ms 50 50 100.00
V2 pulse pwm_rand_output 1.583m 21.875ms 50 50 100.00
V2 blink pwm_rand_output 1.583m 21.875ms 50 50 100.00
V2 heartbeat pwm_rand_output 1.583m 21.875ms 50 50 100.00
V2 resolution pwm_rand_output 1.583m 21.875ms 50 50 100.00
V2 multi_channel pwm_rand_output 1.583m 21.875ms 50 50 100.00
V2 polarity pwm_rand_output 1.583m 21.875ms 50 50 100.00
V2 phase pwm_rand_output 1.583m 21.875ms 50 50 100.00
V2 lowpower pwm_rand_output 1.583m 21.875ms 50 50 100.00
V2 perf pwm_perf 58.000s 10.827ms 50 50 100.00
V2 stress_all pwm_stress_all 4.717m 565.258ms 50 50 100.00
V2 alert_test pwm_alert_test 8.000s 23.859us 50 50 100.00
V2 intr_test pwm_intr_test 7.000s 25.946us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 5.000s 204.949us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 5.000s 204.949us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 7.000s 69.795us 5 5 100.00
pwm_csr_rw 7.000s 31.936us 20 20 100.00
pwm_csr_aliasing 5.000s 104.565us 5 5 100.00
pwm_same_csr_outstanding 13.000s 31.121us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 7.000s 69.795us 5 5 100.00
pwm_csr_rw 7.000s 31.936us 20 20 100.00
pwm_csr_aliasing 5.000s 104.565us 5 5 100.00
pwm_same_csr_outstanding 13.000s 31.121us 20 20 100.00
V2 TOTAL 290 290 100.00
V2S tl_intg_err pwm_tl_intg_err 14.000s 346.088us 20 20 100.00
pwm_sec_cm 5.000s 329.218us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 14.000s 346.088us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 420 420 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 7 100.00
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.46 99.48 99.08 99.84 94.93 94.92 -- 100.00 99.34

Past Results