0cdf265eaa| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 9.000s | 1.086ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 2.000s | 21.986us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 3.000s | 19.353us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 10.000s | 696.076us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 4.000s | 303.907us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 4.000s | 279.759us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 3.000s | 19.353us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 4.000s | 303.907us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 1.567m | 43.746ms | 49 | 50 | 98.00 |
| V2 | pulse | pwm_rand_output | 1.567m | 43.746ms | 49 | 50 | 98.00 |
| V2 | blink | pwm_rand_output | 1.567m | 43.746ms | 49 | 50 | 98.00 |
| V2 | heartbeat | pwm_rand_output | 1.567m | 43.746ms | 49 | 50 | 98.00 |
| V2 | resolution | pwm_rand_output | 1.567m | 43.746ms | 49 | 50 | 98.00 |
| V2 | multi_channel | pwm_rand_output | 1.567m | 43.746ms | 49 | 50 | 98.00 |
| V2 | polarity | pwm_rand_output | 1.567m | 43.746ms | 49 | 50 | 98.00 |
| V2 | phase | pwm_rand_output | 1.567m | 43.746ms | 49 | 50 | 98.00 |
| V2 | lowpower | pwm_rand_output | 1.567m | 43.746ms | 49 | 50 | 98.00 |
| V2 | perf | pwm_perf | 53.000s | 21.433ms | 50 | 50 | 100.00 |
| V2 | stress_all | pwm_stress_all | 4.733m | 47.766ms | 46 | 50 | 92.00 |
| V2 | alert_test | pwm_alert_test | 6.000s | 13.281us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 2.000s | 37.357us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 7.000s | 176.954us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 7.000s | 176.954us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 2.000s | 21.986us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 19.353us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 4.000s | 303.907us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 3.000s | 144.062us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 2.000s | 21.986us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 19.353us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 4.000s | 303.907us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 3.000s | 144.062us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 285 | 290 | 98.28 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 5.000s | 1.339ms | 20 | 20 | 100.00 |
| pwm_sec_cm | 5.000s | 418.255us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 5.000s | 1.339ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 415 | 420 | 98.81 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.37 | 99.41 | 98.95 | 99.84 | 94.65 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 4 failures:
0.pwm_stress_all.29938849556841081524628338624796589841945832996385772803198453818512701988612
Line 300218, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/0.pwm_stress_all/latest/run.log
UVM_ERROR @ 58293681611 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [4] did not MATCH
UVM_INFO @ 58293681611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.pwm_stress_all.22647468548387040763433190802725161056396690627820542265817612847460500153019
Line 74787, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/34.pwm_stress_all/latest/run.log
UVM_ERROR @ 32881936066 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [0] did not MATCH
UVM_INFO @ 32881936066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
9.pwm_rand_output.70467210544644620565708860083996869060218637773103416262733576986686705526177
Line 351, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/9.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---