PWM Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: `5c87d18988`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	6.000s	533.553us	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	61.147us	5	5	100.00
V1	csr_rw	pwm_csr_rw	3.000s	15.945us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	13.000s	500.046us	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	5.000s	380.995us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	4.000s	48.060us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	3.000s	15.945us	20	20	100.00
		pwm_csr_aliasing	5.000s	380.995us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.517m	21.878ms	50	50	100.00
V2	pulse	pwm_rand_output	1.517m	21.878ms	50	50	100.00
V2	blink	pwm_rand_output	1.517m	21.878ms	50	50	100.00
V2	heartbeat	pwm_rand_output	1.517m	21.878ms	50	50	100.00
V2	resolution	pwm_rand_output	1.517m	21.878ms	50	50	100.00
V2	multi_channel	pwm_rand_output	1.517m	21.878ms	50	50	100.00
V2	polarity	pwm_rand_output	1.517m	21.878ms	50	50	100.00
V2	phase	pwm_rand_output	1.517m	21.878ms	50	50	100.00
V2	lowpower	pwm_rand_output	1.517m	21.878ms	50	50	100.00
V2	perf	pwm_perf	51.000s	10.716ms	50	50	100.00
V2	stress_all	pwm_stress_all	4.950m	85.026ms	47	50	94.00
V2	alert_test	pwm_alert_test	4.000s	27.267us	50	50	100.00
V2	intr_test	pwm_intr_test	3.000s	19.450us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	7.000s	463.670us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	7.000s	463.670us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	61.147us	5	5	100.00
		pwm_csr_rw	3.000s	15.945us	20	20	100.00
		pwm_csr_aliasing	5.000s	380.995us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	145.573us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	61.147us	5	5	100.00
		pwm_csr_rw	3.000s	15.945us	20	20	100.00
		pwm_csr_aliasing	5.000s	380.995us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	145.573us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	pwm_tl_intg_err	6.000s	1.128ms	20	20	100.00
		pwm_sec_cm	4.000s	128.423us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	6.000s	1.128ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			417	420	99.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.34	99.31	98.77	99.92	94.59	94.92	--	100.00	99.34

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 3 failures:

Test pwm_stress_all has 3 failures.

0.pwm_stress_all.36276993582336016522234124004148362085696938952725167235652446381482169529588
Line 559860, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/0.pwm_stress_all/latest/run.log

  UVM_ERROR @ 134518151120 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [2] did not MATCH
  UVM_INFO @ 134518151120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.pwm_stress_all.96276866376166867335553190511553820095783250287282809342298192126387864683394
Line 480, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/4.pwm_stress_all/latest/run.log

  UVM_ERROR @ 149888147621 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [1] did not MATCH
  UVM_INFO @ 149888147621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.