PWM Simulation Results

Wednesday February 14 2024 20:02:28 UTC

GitHub Revision: 93b7cb99d8

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 53669536132820869698500732458181248593474076177124168900566436467251403141328

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	6.000s	5.658ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	17.767us	5	5	100.00
V1	csr_rw	pwm_csr_rw	3.000s	83.244us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	10.000s	645.045us	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	5.000s	37.490us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	5.000s	38.933us	2	20	10.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	3.000s	83.244us	20	20	100.00
		pwm_csr_aliasing	5.000s	37.490us	5	5	100.00
V1		TOTAL			87	105	82.86
V2	dutycycle	pwm_rand_output	1.100m	21.879ms	48	50	96.00
V2	pulse	pwm_rand_output	1.100m	21.879ms	48	50	96.00
V2	blink	pwm_rand_output	1.100m	21.879ms	48	50	96.00
V2	heartbeat	pwm_rand_output	1.100m	21.879ms	48	50	96.00
V2	resolution	pwm_rand_output	1.100m	21.879ms	48	50	96.00
V2	multi_channel	pwm_rand_output	1.100m	21.879ms	48	50	96.00
V2	polarity	pwm_rand_output	1.100m	21.879ms	48	50	96.00
V2	phase	pwm_rand_output	1.100m	21.879ms	48	50	96.00
V2	lowpower	pwm_rand_output	1.100m	21.879ms	48	50	96.00
V2	perf	pwm_perf	51.000s	21.874ms	50	50	100.00
V2	stress_all	pwm_stress_all	3.883m	43.919ms	50	50	100.00
V2	alert_test	pwm_alert_test	4.000s	16.088us	50	50	100.00
V2	intr_test	pwm_intr_test	4.000s	14.500us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	6.000s	877.924us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	6.000s	877.924us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	17.767us	5	5	100.00
		pwm_csr_rw	3.000s	83.244us	20	20	100.00
		pwm_csr_aliasing	5.000s	37.490us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	89.017us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	17.767us	5	5	100.00
		pwm_csr_rw	3.000s	83.244us	20	20	100.00
		pwm_csr_aliasing	5.000s	37.490us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	89.017us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	pwm_tl_intg_err	5.000s	321.237us	20	20	100.00
		pwm_sec_cm	3.000s	75.480us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	5.000s	321.237us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			400	420	95.24

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	6	85.71
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.40	99.41	98.95	99.76	94.93	94.92	--	100.00	99.01

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:757) [pwm_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 10 failures:
  • Test pwm_csr_mem_rw_with_rand_reset has 10 failures.

    • 3.pwm_csr_mem_rw_with_rand_reset.11046455840962484294705974468158572453662121325274962592496227816874946681974
      Line 583, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/3.pwm_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  14683286 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.pwm_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
        UVM_INFO @  14683286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.pwm_csr_mem_rw_with_rand_reset.4278944415918623859114817473803153606708897809458676607942032885436284508520
      Line 739, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/6.pwm_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  62935859 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.pwm_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
        UVM_INFO @  62935859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 8 more failures.

• Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:757) [pwm_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 8 failures:
  • Test pwm_csr_mem_rw_with_rand_reset has 8 failures.

    • 0.pwm_csr_mem_rw_with_rand_reset.10821816723068244642438622289957872324708952462476871367764927516032891964970
      Line 700, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/0.pwm_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  35903995 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.pwm_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
        UVM_INFO @  35903995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.pwm_csr_mem_rw_with_rand_reset.53328339186782567740207628765819125013606841209481694744395172089097890557761
      Line 594, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/1.pwm_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @  94021771 ps: (cip_base_vseq.sv:757) [uvm_test_top.env.virtual_sequencer.pwm_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
        UVM_INFO @  94021771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 6 more failures.

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
  • Test pwm_rand_output has 2 failures.

    • 21.pwm_rand_output.30075579521660224914904246852239694765952841493249528071642764778708039448893
      Line 401, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/21.pwm_rand_output/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 36.pwm_rand_output.26314310083285206128819262082375329268515937644410858863811948640979919381520
      Line 402, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/36.pwm_rand_output/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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