49a27e136c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 9.000s | 2.128ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 2.000s | 18.880us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 3.000s | 19.055us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 11.000s | 699.394us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 4.000s | 936.285us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 3.000s | 37.292us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 3.000s | 19.055us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 4.000s | 936.285us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 1.667m | 80.763ms | 48 | 50 | 96.00 |
| V2 | pulse | pwm_rand_output | 1.667m | 80.763ms | 48 | 50 | 96.00 |
| V2 | blink | pwm_rand_output | 1.667m | 80.763ms | 48 | 50 | 96.00 |
| V2 | heartbeat | pwm_rand_output | 1.667m | 80.763ms | 48 | 50 | 96.00 |
| V2 | resolution | pwm_rand_output | 1.667m | 80.763ms | 48 | 50 | 96.00 |
| V2 | multi_channel | pwm_rand_output | 1.667m | 80.763ms | 48 | 50 | 96.00 |
| V2 | polarity | pwm_rand_output | 1.667m | 80.763ms | 48 | 50 | 96.00 |
| V2 | phase | pwm_rand_output | 1.667m | 80.763ms | 48 | 50 | 96.00 |
| V2 | lowpower | pwm_rand_output | 1.667m | 80.763ms | 48 | 50 | 96.00 |
| V2 | perf | pwm_perf | 49.000s | 50.000ms | 50 | 50 | 100.00 |
| V2 | stress_all | pwm_stress_all | 4.433m | 74.003ms | 44 | 50 | 88.00 |
| V2 | alert_test | pwm_alert_test | 3.000s | 46.696us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 4.000s | 13.253us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 6.000s | 484.880us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 6.000s | 484.880us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 2.000s | 18.880us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 19.055us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 4.000s | 936.285us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 4.000s | 60.292us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 2.000s | 18.880us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 19.055us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 4.000s | 936.285us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 4.000s | 60.292us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 282 | 290 | 97.24 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 5.000s | 389.064us | 20 | 20 | 100.00 |
| pwm_sec_cm | 3.000s | 43.483us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 5.000s | 389.064us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 412 | 420 | 98.10 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.46 | 99.41 | 98.95 | 99.92 | 94.96 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 6 failures:
3.pwm_stress_all.107126760778857327446077157451746591942138035613363859475884172019905038925977
Line 708, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/3.pwm_stress_all/latest/run.log
UVM_ERROR @ 420104625508 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [4] did not MATCH
UVM_INFO @ 420104625508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.pwm_stress_all.48060906487171810276884736983802949381510192446461357882617818118164060768750
Line 262932, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/16.pwm_stress_all/latest/run.log
UVM_ERROR @ 43179202403 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [1] did not MATCH
UVM_INFO @ 43179202403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
21.pwm_rand_output.73678178810304995298555565952210496317004862957491084281472494806783213701656
Line 3199761, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/21.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.pwm_rand_output.820393585494661735455870509291281883712474075337801959756126039580040024282
Line 100192, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/38.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---