PWM Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: `c30684b3ca`

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	9.000s	1.064ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	18.438us	5	5	100.00
V1	csr_rw	pwm_csr_rw	12.000s	244.623us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	13.000s	1.030ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	83.243us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	4.000s	98.984us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	12.000s	244.623us	20	20	100.00
		pwm_csr_aliasing	4.000s	83.243us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	2.317m	11.173ms	50	50	100.00
V2	pulse	pwm_rand_output	2.317m	11.173ms	50	50	100.00
V2	blink	pwm_rand_output	2.317m	11.173ms	50	50	100.00
V2	heartbeat	pwm_rand_output	2.317m	11.173ms	50	50	100.00
V2	resolution	pwm_rand_output	2.317m	11.173ms	50	50	100.00
V2	multi_channel	pwm_rand_output	2.317m	11.173ms	50	50	100.00
V2	polarity	pwm_rand_output	2.317m	11.173ms	50	50	100.00
V2	phase	pwm_rand_output	2.317m	11.173ms	50	50	100.00
V2	lowpower	pwm_rand_output	2.317m	11.173ms	50	50	100.00
V2	perf	pwm_perf	52.000s	10.720ms	49	50	98.00
V2	stress_all	pwm_stress_all	4.250m	54.049ms	49	50	98.00
V2	alert_test	pwm_alert_test	6.000s	41.562us	50	50	100.00
V2	intr_test	pwm_intr_test	4.000s	21.222us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	14.000s	53.171us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	14.000s	53.171us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	18.438us	5	5	100.00
		pwm_csr_rw	12.000s	244.623us	20	20	100.00
		pwm_csr_aliasing	4.000s	83.243us	5	5	100.00
		pwm_same_csr_outstanding	13.000s	784.222us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	18.438us	5	5	100.00
		pwm_csr_rw	12.000s	244.623us	20	20	100.00
		pwm_csr_aliasing	4.000s	83.243us	5	5	100.00
		pwm_same_csr_outstanding	13.000s	784.222us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	pwm_tl_intg_err	19.000s	94.926us	20	20	100.00
		pwm_sec_cm	6.000s	140.715us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	19.000s	94.926us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			418	420	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.37	99.41	98.95	99.80	94.72	94.92	--	100.00	99.01

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pwm_perf has 1 failures.
  - 32.pwm_perf.105569788155058854107074152385193845979202980845190694676777436614841034379891
    Line 379, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/32.pwm_perf/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 1 failures:
- Test pwm_stress_all has 1 failures.
  - 34.pwm_stress_all.25095724209227796809722608139145387648042796194212602819201289789151814194092
    Line 131648, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/34.pwm_stress_all/latest/run.log
```
  UVM_ERROR @ 40229556206 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 40229556206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

PWM Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: c30684b3ca

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `c30684b3ca`