8d1fda3660| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 15.000s | 533.280us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 5.000s | 129.087us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 5.000s | 31.743us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 15.000s | 1.340ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 5.000s | 57.378us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 6.000s | 100.859us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 5.000s | 31.743us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 5.000s | 57.378us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 1.250m | 10.609ms | 50 | 50 | 100.00 |
| V2 | pulse | pwm_rand_output | 1.250m | 10.609ms | 50 | 50 | 100.00 |
| V2 | blink | pwm_rand_output | 1.250m | 10.609ms | 50 | 50 | 100.00 |
| V2 | heartbeat | pwm_rand_output | 1.250m | 10.609ms | 50 | 50 | 100.00 |
| V2 | resolution | pwm_rand_output | 1.250m | 10.609ms | 50 | 50 | 100.00 |
| V2 | multi_channel | pwm_rand_output | 1.250m | 10.609ms | 50 | 50 | 100.00 |
| V2 | polarity | pwm_rand_output | 1.250m | 10.609ms | 50 | 50 | 100.00 |
| V2 | phase | pwm_rand_output | 1.250m | 10.609ms | 50 | 50 | 100.00 |
| V2 | lowpower | pwm_rand_output | 1.250m | 10.609ms | 50 | 50 | 100.00 |
| V2 | perf | pwm_perf | 58.000s | 10.941ms | 49 | 50 | 98.00 |
| V2 | stress_all | pwm_stress_all | 4.167m | 74.992ms | 49 | 50 | 98.00 |
| V2 | alert_test | pwm_alert_test | 9.000s | 13.611us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 6.000s | 71.471us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 7.000s | 86.663us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 7.000s | 86.663us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 5.000s | 129.087us | 5 | 5 | 100.00 |
| pwm_csr_rw | 5.000s | 31.743us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 5.000s | 57.378us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 4.000s | 44.844us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 5.000s | 129.087us | 5 | 5 | 100.00 |
| pwm_csr_rw | 5.000s | 31.743us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 5.000s | 57.378us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 4.000s | 44.844us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 288 | 290 | 99.31 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 7.000s | 1.516ms | 20 | 20 | 100.00 |
| pwm_sec_cm | 3.000s | 37.045us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 7.000s | 1.516ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 418 | 420 | 99.52 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.37 | 99.38 | 98.89 | 99.84 | 94.76 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 1 failures:
23.pwm_stress_all.13068352344632120830562006759176979608769799037381787891471053108842380689735
Line 2777, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/23.pwm_stress_all/latest/run.log
UVM_ERROR @ 33069862577 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [4] did not MATCH
UVM_INFO @ 33069862577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
40.pwm_perf.101844494339642574329994616591237412617338106972131914210501972943991190828095
Line 329, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/40.pwm_perf/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---