b938dde05c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 10.000s | 1.818ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 3.000s | 16.679us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 4.000s | 78.035us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 11.000s | 244.639us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 5.000s | 37.784us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 4.000s | 38.776us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 4.000s | 78.035us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 5.000s | 37.784us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 2.600m | 43.758ms | 49 | 50 | 98.00 |
| V2 | pulse | pwm_rand_output | 2.600m | 43.758ms | 49 | 50 | 98.00 |
| V2 | blink | pwm_rand_output | 2.600m | 43.758ms | 49 | 50 | 98.00 |
| V2 | heartbeat | pwm_rand_output | 2.600m | 43.758ms | 49 | 50 | 98.00 |
| V2 | resolution | pwm_rand_output | 2.600m | 43.758ms | 49 | 50 | 98.00 |
| V2 | multi_channel | pwm_rand_output | 2.600m | 43.758ms | 49 | 50 | 98.00 |
| V2 | polarity | pwm_rand_output | 2.600m | 43.758ms | 49 | 50 | 98.00 |
| V2 | phase | pwm_rand_output | 2.600m | 43.758ms | 49 | 50 | 98.00 |
| V2 | lowpower | pwm_rand_output | 2.600m | 43.758ms | 49 | 50 | 98.00 |
| V2 | perf | pwm_perf | 51.000s | 10.502ms | 50 | 50 | 100.00 |
| V2 | stress_all | pwm_stress_all | 5.967m | 77.371ms | 47 | 50 | 94.00 |
| V2 | alert_test | pwm_alert_test | 8.000s | 11.836us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 3.000s | 11.063us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 7.000s | 222.442us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 7.000s | 222.442us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 3.000s | 16.679us | 5 | 5 | 100.00 |
| pwm_csr_rw | 4.000s | 78.035us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 5.000s | 37.784us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 5.000s | 33.734us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 3.000s | 16.679us | 5 | 5 | 100.00 |
| pwm_csr_rw | 4.000s | 78.035us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 5.000s | 37.784us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 5.000s | 33.734us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 286 | 290 | 98.62 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 6.000s | 546.615us | 20 | 20 | 100.00 |
| pwm_sec_cm | 3.000s | 44.634us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 6.000s | 546.615us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 416 | 420 | 99.05 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.42 | 99.38 | 98.89 | 99.92 | 94.83 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 3 failures:
14.pwm_stress_all.88658278037132830551535424916423340128258805211094000609725379531703270384103
Line 977, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/14.pwm_stress_all/latest/run.log
UVM_ERROR @ 22021317833 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [4] did not MATCH
UVM_INFO @ 22021317833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.pwm_stress_all.30395998691446212400390970808067010583586139157570522137060788645682399509511
Line 503, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/34.pwm_stress_all/latest/run.log
UVM_ERROR @ 16612135858 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [0] did not MATCH
UVM_INFO @ 16612135858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
46.pwm_rand_output.75386476187639350016378035327271118715082357835336818638122943007806132600013
Line 4241, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/46.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---