PWM Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: 9f4903e77a

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 15.000s 530.197us 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 8.000s 69.825us 5 5 100.00
V1 csr_rw pwm_csr_rw 12.000s 83.386us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 15.000s 1.829ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 13.000s 50.194us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 12.000s 32.882us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 12.000s 83.386us 20 20 100.00
pwm_csr_aliasing 13.000s 50.194us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 2.517m 33.866ms 50 50 100.00
V2 pulse pwm_rand_output 2.517m 33.866ms 50 50 100.00
V2 blink pwm_rand_output 2.517m 33.866ms 50 50 100.00
V2 heartbeat pwm_rand_output 2.517m 33.866ms 50 50 100.00
V2 resolution pwm_rand_output 2.517m 33.866ms 50 50 100.00
V2 multi_channel pwm_rand_output 2.517m 33.866ms 50 50 100.00
V2 polarity pwm_rand_output 2.517m 33.866ms 50 50 100.00
V2 phase pwm_rand_output 2.517m 33.866ms 50 50 100.00
V2 lowpower pwm_rand_output 2.517m 33.866ms 50 50 100.00
V2 perf pwm_perf 57.000s 10.942ms 50 50 100.00
V2 stress_all pwm_stress_all 5.833m 306.173ms 49 50 98.00
V2 alert_test pwm_alert_test 12.000s 15.808us 50 50 100.00
V2 intr_test pwm_intr_test 17.000s 19.993us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 13.000s 77.153us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 13.000s 77.153us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 8.000s 69.825us 5 5 100.00
pwm_csr_rw 12.000s 83.386us 20 20 100.00
pwm_csr_aliasing 13.000s 50.194us 5 5 100.00
pwm_same_csr_outstanding 12.000s 178.175us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 8.000s 69.825us 5 5 100.00
pwm_csr_rw 12.000s 83.386us 20 20 100.00
pwm_csr_aliasing 13.000s 50.194us 5 5 100.00
pwm_same_csr_outstanding 12.000s 178.175us 20 20 100.00
V2 TOTAL 289 290 99.66
V2S tl_intg_err pwm_tl_intg_err 8.000s 302.316us 20 20 100.00
pwm_sec_cm 3.000s 97.134us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 8.000s 302.316us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 419 420 99.76

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.32 99.28 98.71 99.92 94.59 94.92 -- 100.00 99.01

Failure Buckets

Past Results