PWM Simulation Results

Thursday April 11 2024 19:07:25 UTC

GitHub Revision: 1f410ef5dc

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 77676901304510083363507443373754332549719316834151559528665885252978172929472

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 6.000s 523.096us 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 3.000s 14.808us 5 5 100.00
V1 csr_rw pwm_csr_rw 3.000s 17.584us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 12.000s 1.973ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 5.000s 613.441us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 4.000s 52.379us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 3.000s 17.584us 20 20 100.00
pwm_csr_aliasing 5.000s 613.441us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.817m 10.941ms 49 50 98.00
V2 pulse pwm_rand_output 1.817m 10.941ms 49 50 98.00
V2 blink pwm_rand_output 1.817m 10.941ms 49 50 98.00
V2 heartbeat pwm_rand_output 1.817m 10.941ms 49 50 98.00
V2 resolution pwm_rand_output 1.817m 10.941ms 49 50 98.00
V2 multi_channel pwm_rand_output 1.817m 10.941ms 49 50 98.00
V2 polarity pwm_rand_output 1.817m 10.941ms 49 50 98.00
V2 phase pwm_rand_output 1.817m 10.941ms 49 50 98.00
V2 lowpower pwm_rand_output 1.817m 10.941ms 49 50 98.00
V2 perf pwm_perf 52.000s 42.003ms 48 50 96.00
V2 stress_all pwm_stress_all 4.683m 54.693ms 45 50 90.00
V2 alert_test pwm_alert_test 4.000s 43.408us 50 50 100.00
V2 intr_test pwm_intr_test 4.000s 116.725us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 6.000s 40.312us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 6.000s 40.312us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 3.000s 14.808us 5 5 100.00
pwm_csr_rw 3.000s 17.584us 20 20 100.00
pwm_csr_aliasing 5.000s 613.441us 5 5 100.00
pwm_same_csr_outstanding 4.000s 176.543us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 3.000s 14.808us 5 5 100.00
pwm_csr_rw 3.000s 17.584us 20 20 100.00
pwm_csr_aliasing 5.000s 613.441us 5 5 100.00
pwm_same_csr_outstanding 4.000s 176.543us 20 20 100.00
V2 TOTAL 282 290 97.24
V2S tl_intg_err pwm_tl_intg_err 6.000s 229.558us 20 20 100.00
pwm_sec_cm 3.000s 76.505us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 6.000s 229.558us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 412 420 98.10

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 4 57.14
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.21 99.24 98.65 99.72 94.48 94.92 -- 100.00 99.01

Failure Buckets

Past Results