PWM Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: d3942ca074

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 7.000s 2.551ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 4.000s 75.683us 5 5 100.00
V1 csr_rw pwm_csr_rw 4.000s 46.604us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 11.000s 4.595ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 5.000s 35.071us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 4.000s 94.605us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 4.000s 46.604us 20 20 100.00
pwm_csr_aliasing 5.000s 35.071us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.417m 10.829ms 50 50 100.00
V2 pulse pwm_rand_output 1.417m 10.829ms 50 50 100.00
V2 blink pwm_rand_output 1.417m 10.829ms 50 50 100.00
V2 heartbeat pwm_rand_output 1.417m 10.829ms 50 50 100.00
V2 resolution pwm_rand_output 1.417m 10.829ms 50 50 100.00
V2 multi_channel pwm_rand_output 1.417m 10.829ms 50 50 100.00
V2 polarity pwm_rand_output 1.417m 10.829ms 50 50 100.00
V2 phase pwm_rand_output 1.417m 10.829ms 50 50 100.00
V2 lowpower pwm_rand_output 1.417m 10.829ms 50 50 100.00
V2 perf pwm_perf 54.000s 43.760ms 50 50 100.00
V2 stress_all pwm_stress_all 5.217m 73.489ms 47 50 94.00
V2 alert_test pwm_alert_test 4.000s 83.087us 50 50 100.00
V2 intr_test pwm_intr_test 4.000s 12.377us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 6.000s 383.279us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 6.000s 383.279us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 4.000s 75.683us 5 5 100.00
pwm_csr_rw 4.000s 46.604us 20 20 100.00
pwm_csr_aliasing 5.000s 35.071us 5 5 100.00
pwm_same_csr_outstanding 5.000s 97.905us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 4.000s 75.683us 5 5 100.00
pwm_csr_rw 4.000s 46.604us 20 20 100.00
pwm_csr_aliasing 5.000s 35.071us 5 5 100.00
pwm_same_csr_outstanding 5.000s 97.905us 20 20 100.00
V2 TOTAL 287 290 98.97
V2S tl_intg_err pwm_tl_intg_err 7.000s 687.143us 20 20 100.00
pwm_sec_cm 3.000s 112.231us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 7.000s 687.143us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 417 420 99.29

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.30 99.45 99.01 99.72 94.48 94.92 -- 100.00 99.01

Failure Buckets

Past Results