d3942ca074
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | pwm_smoke | 7.000s | 2.551ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | pwm_csr_hw_reset | 4.000s | 75.683us | 5 | 5 | 100.00 |
V1 | csr_rw | pwm_csr_rw | 4.000s | 46.604us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | pwm_csr_bit_bash | 11.000s | 4.595ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | pwm_csr_aliasing | 5.000s | 35.071us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 4.000s | 94.605us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 4.000s | 46.604us | 20 | 20 | 100.00 |
pwm_csr_aliasing | 5.000s | 35.071us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | dutycycle | pwm_rand_output | 1.417m | 10.829ms | 50 | 50 | 100.00 |
V2 | pulse | pwm_rand_output | 1.417m | 10.829ms | 50 | 50 | 100.00 |
V2 | blink | pwm_rand_output | 1.417m | 10.829ms | 50 | 50 | 100.00 |
V2 | heartbeat | pwm_rand_output | 1.417m | 10.829ms | 50 | 50 | 100.00 |
V2 | resolution | pwm_rand_output | 1.417m | 10.829ms | 50 | 50 | 100.00 |
V2 | multi_channel | pwm_rand_output | 1.417m | 10.829ms | 50 | 50 | 100.00 |
V2 | polarity | pwm_rand_output | 1.417m | 10.829ms | 50 | 50 | 100.00 |
V2 | phase | pwm_rand_output | 1.417m | 10.829ms | 50 | 50 | 100.00 |
V2 | lowpower | pwm_rand_output | 1.417m | 10.829ms | 50 | 50 | 100.00 |
V2 | perf | pwm_perf | 54.000s | 43.760ms | 50 | 50 | 100.00 |
V2 | stress_all | pwm_stress_all | 5.217m | 73.489ms | 47 | 50 | 94.00 |
V2 | alert_test | pwm_alert_test | 4.000s | 83.087us | 50 | 50 | 100.00 |
V2 | intr_test | pwm_intr_test | 4.000s | 12.377us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | pwm_tl_errors | 6.000s | 383.279us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | pwm_tl_errors | 6.000s | 383.279us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 4.000s | 75.683us | 5 | 5 | 100.00 |
pwm_csr_rw | 4.000s | 46.604us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 5.000s | 35.071us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 5.000s | 97.905us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | pwm_csr_hw_reset | 4.000s | 75.683us | 5 | 5 | 100.00 |
pwm_csr_rw | 4.000s | 46.604us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 5.000s | 35.071us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 5.000s | 97.905us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 287 | 290 | 98.97 | |||
V2S | tl_intg_err | pwm_tl_intg_err | 7.000s | 687.143us | 20 | 20 | 100.00 |
pwm_sec_cm | 3.000s | 112.231us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 7.000s | 687.143us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 417 | 420 | 99.29 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 7 | 7 | 6 | 85.71 |
V2S | 2 | 2 | 2 | 100.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
98.30 | 99.45 | 99.01 | 99.72 | 94.48 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard]
has 3 failures:
2.pwm_stress_all.78512280570991308026150753249814557005912891162385801041831579061234458895777
Line 699941, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/2.pwm_stress_all/latest/run.log
UVM_ERROR @ 62208859735 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [2] did not MATCH
UVM_INFO @ 62208859735 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.pwm_stress_all.5016883794027333622065105608468392151420876038514528224048255212772912627072
Line 523286, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/13.pwm_stress_all/latest/run.log
UVM_ERROR @ 61560238078 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [0] did not MATCH
UVM_INFO @ 61560238078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.