PWM Simulation Results

Sunday April 07 2024 19:02:41 UTC

GitHub Revision: 7773b039d0

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 110372901762865644007400082009110088154180821215015477169464044145224727696933

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 14.000s 536.388us 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 7.000s 22.219us 5 5 100.00
V1 csr_rw pwm_csr_rw 8.000s 14.630us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 11.000s 1.400ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 9.000s 77.175us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 8.000s 305.831us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 8.000s 14.630us 20 20 100.00
pwm_csr_aliasing 9.000s 77.175us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 2.917m 20.591ms 49 50 98.00
V2 pulse pwm_rand_output 2.917m 20.591ms 49 50 98.00
V2 blink pwm_rand_output 2.917m 20.591ms 49 50 98.00
V2 heartbeat pwm_rand_output 2.917m 20.591ms 49 50 98.00
V2 resolution pwm_rand_output 2.917m 20.591ms 49 50 98.00
V2 multi_channel pwm_rand_output 2.917m 20.591ms 49 50 98.00
V2 polarity pwm_rand_output 2.917m 20.591ms 49 50 98.00
V2 phase pwm_rand_output 2.917m 20.591ms 49 50 98.00
V2 lowpower pwm_rand_output 2.917m 20.591ms 49 50 98.00
V2 perf pwm_perf 57.000s 42.001ms 49 50 98.00
V2 stress_all pwm_stress_all 4.500m 262.485ms 50 50 100.00
V2 alert_test pwm_alert_test 12.000s 45.864us 50 50 100.00
V2 intr_test pwm_intr_test 8.000s 58.314us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 9.000s 481.667us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 9.000s 481.667us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 7.000s 22.219us 5 5 100.00
pwm_csr_rw 8.000s 14.630us 20 20 100.00
pwm_csr_aliasing 9.000s 77.175us 5 5 100.00
pwm_same_csr_outstanding 12.000s 55.295us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 7.000s 22.219us 5 5 100.00
pwm_csr_rw 8.000s 14.630us 20 20 100.00
pwm_csr_aliasing 9.000s 77.175us 5 5 100.00
pwm_same_csr_outstanding 12.000s 55.295us 20 20 100.00
V2 TOTAL 288 290 99.31
V2S tl_intg_err pwm_tl_intg_err 14.000s 217.213us 20 20 100.00
pwm_sec_cm 8.000s 123.173us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 14.000s 217.213us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 418 420 99.52

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 5 71.43
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.55 99.55 99.20 99.92 95.10 94.92 -- 100.00 99.01

Failure Buckets

Past Results