ae68723071| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 5.000s | 1.106ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 3.000s | 20.345us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 7.000s | 69.725us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 10.000s | 5.299ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 4.000s | 172.035us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 7.000s | 72.306us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 7.000s | 69.725us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 4.000s | 172.035us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 2.567m | 10.944ms | 49 | 50 | 98.00 |
| V2 | pulse | pwm_rand_output | 2.567m | 10.944ms | 49 | 50 | 98.00 |
| V2 | blink | pwm_rand_output | 2.567m | 10.944ms | 49 | 50 | 98.00 |
| V2 | heartbeat | pwm_rand_output | 2.567m | 10.944ms | 49 | 50 | 98.00 |
| V2 | resolution | pwm_rand_output | 2.567m | 10.944ms | 49 | 50 | 98.00 |
| V2 | multi_channel | pwm_rand_output | 2.567m | 10.944ms | 49 | 50 | 98.00 |
| V2 | polarity | pwm_rand_output | 2.567m | 10.944ms | 49 | 50 | 98.00 |
| V2 | phase | pwm_rand_output | 2.567m | 10.944ms | 49 | 50 | 98.00 |
| V2 | lowpower | pwm_rand_output | 2.567m | 10.944ms | 49 | 50 | 98.00 |
| V2 | perf | pwm_perf | 51.000s | 21.004ms | 47 | 50 | 94.00 |
| V2 | stress_all | pwm_stress_all | 4.167m | 80.015ms | 47 | 50 | 94.00 |
| V2 | alert_test | pwm_alert_test | 3.000s | 15.197us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 12.000s | 13.827us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 14.000s | 332.186us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 14.000s | 332.186us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 3.000s | 20.345us | 5 | 5 | 100.00 |
| pwm_csr_rw | 7.000s | 69.725us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 4.000s | 172.035us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 13.000s | 82.208us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 3.000s | 20.345us | 5 | 5 | 100.00 |
| pwm_csr_rw | 7.000s | 69.725us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 4.000s | 172.035us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 13.000s | 82.208us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 283 | 290 | 97.59 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 9.000s | 129.377us | 20 | 20 | 100.00 |
| pwm_sec_cm | 3.000s | 65.386us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 9.000s | 129.377us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 413 | 420 | 98.33 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 4 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.49 | 99.52 | 99.14 | 99.84 | 95.03 | 94.92 | -- | 100.00 | 99.01 |
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
5.pwm_perf.70716619982921668364317144984802067372486947009498563199426412950320925875082
Line 399, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/5.pwm_perf/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.pwm_perf.81880618902055603908214764566280308741873897502791660598756244576215378817510
Line 399, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/13.pwm_perf/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
36.pwm_rand_output.114549184674888955553992129598663712995080545301097356905907552251985250091014
Line 354, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/36.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 3 failures:
13.pwm_stress_all.55104050915052242356566009175171025849267472562722893619484009671649382086574
Line 854, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/13.pwm_stress_all/latest/run.log
UVM_ERROR @ 133387798212 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [5] did not MATCH
UVM_INFO @ 133387798212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.pwm_stress_all.91242389164664890765594017072014537238732582830752467062962759107234148287834
Line 4782051, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/36.pwm_stress_all/latest/run.log
UVM_ERROR @ 20995769557 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [5] did not MATCH
UVM_INFO @ 20995769557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.