0cb61fc7e7| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 5.000s | 877.761us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 3.000s | 47.018us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 3.000s | 14.986us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 10.000s | 2.658ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 4.000s | 140.015us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 3.000s | 21.766us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 3.000s | 14.986us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 4.000s | 140.015us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 1.067m | 10.717ms | 50 | 50 | 100.00 |
| V2 | pulse | pwm_rand_output | 1.067m | 10.717ms | 50 | 50 | 100.00 |
| V2 | blink | pwm_rand_output | 1.067m | 10.717ms | 50 | 50 | 100.00 |
| V2 | heartbeat | pwm_rand_output | 1.067m | 10.717ms | 50 | 50 | 100.00 |
| V2 | resolution | pwm_rand_output | 1.067m | 10.717ms | 50 | 50 | 100.00 |
| V2 | multi_channel | pwm_rand_output | 1.067m | 10.717ms | 50 | 50 | 100.00 |
| V2 | polarity | pwm_rand_output | 1.067m | 10.717ms | 50 | 50 | 100.00 |
| V2 | phase | pwm_rand_output | 1.067m | 10.717ms | 50 | 50 | 100.00 |
| V2 | lowpower | pwm_rand_output | 1.067m | 10.717ms | 50 | 50 | 100.00 |
| V2 | perf | pwm_perf | 54.000s | 47.731ms | 49 | 50 | 98.00 |
| V2 | stress_all | pwm_stress_all | 4.783m | 53.008ms | 45 | 50 | 90.00 |
| V2 | alert_test | pwm_alert_test | 3.000s | 50.019us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 3.000s | 41.745us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 9.000s | 310.138us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 9.000s | 310.138us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 3.000s | 47.018us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 14.986us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 4.000s | 140.015us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 7.000s | 382.242us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 3.000s | 47.018us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 14.986us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 4.000s | 140.015us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 7.000s | 382.242us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 284 | 290 | 97.93 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 10.000s | 170.157us | 20 | 20 | 100.00 |
| pwm_sec_cm | 3.000s | 110.510us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 10.000s | 170.157us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 414 | 420 | 98.57 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.34 | 99.28 | 98.71 | 99.92 | 94.65 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 5 failures:
6.pwm_stress_all.41209590694380635097608403611902758847949231321103120194266776046566145966739
Line 8916, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/6.pwm_stress_all/latest/run.log
UVM_ERROR @ 90176656187 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [3] did not MATCH
UVM_INFO @ 90176656187 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.pwm_stress_all.42040052585041849473642613111601056238942926462599892847881784930219267337980
Line 4520469, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/11.pwm_stress_all/latest/run.log
UVM_ERROR @ 48453217396 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [0] did not MATCH
UVM_INFO @ 48453217396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
16.pwm_perf.29870468412787116339947017769319579198116288759906432066065164348405769056510
Line 375, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/16.pwm_perf/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---