PWM Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: ecd9f08747

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 10.000s 2.311ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 3.000s 17.771us 5 5 100.00
V1 csr_rw pwm_csr_rw 3.000s 70.991us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 10.000s 1.336ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 5.000s 404.879us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 4.000s 25.494us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 3.000s 70.991us 20 20 100.00
pwm_csr_aliasing 5.000s 404.879us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 55.000s 43.757ms 50 50 100.00
V2 pulse pwm_rand_output 55.000s 43.757ms 50 50 100.00
V2 blink pwm_rand_output 55.000s 43.757ms 50 50 100.00
V2 heartbeat pwm_rand_output 55.000s 43.757ms 50 50 100.00
V2 resolution pwm_rand_output 55.000s 43.757ms 50 50 100.00
V2 multi_channel pwm_rand_output 55.000s 43.757ms 50 50 100.00
V2 polarity pwm_rand_output 55.000s 43.757ms 50 50 100.00
V2 phase pwm_rand_output 55.000s 43.757ms 50 50 100.00
V2 lowpower pwm_rand_output 55.000s 43.757ms 50 50 100.00
V2 perf pwm_perf 1.000m 10.612ms 50 50 100.00
V2 stress_all pwm_stress_all 3.967m 222.967ms 49 50 98.00
V2 alert_test pwm_alert_test 4.000s 90.139us 50 50 100.00
V2 intr_test pwm_intr_test 3.000s 13.311us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 6.000s 40.194us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 6.000s 40.194us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 3.000s 17.771us 5 5 100.00
pwm_csr_rw 3.000s 70.991us 20 20 100.00
pwm_csr_aliasing 5.000s 404.879us 5 5 100.00
pwm_same_csr_outstanding 4.000s 35.818us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 3.000s 17.771us 5 5 100.00
pwm_csr_rw 3.000s 70.991us 20 20 100.00
pwm_csr_aliasing 5.000s 404.879us 5 5 100.00
pwm_same_csr_outstanding 4.000s 35.818us 20 20 100.00
V2 TOTAL 289 290 99.66
V2S tl_intg_err pwm_tl_intg_err 5.000s 217.828us 20 20 100.00
pwm_sec_cm 3.000s 72.428us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 5.000s 217.828us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 419 420 99.76

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.16 99.10 98.40 99.76 94.45 94.92 -- 100.00 99.01

Failure Buckets

Past Results