PWM Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: 349bab6601

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 11.000s 537.118us 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 3.000s 21.195us 5 5 100.00
V1 csr_rw pwm_csr_rw 3.000s 18.594us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 6.000s 1.205ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 3.000s 139.689us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 3.000s 26.781us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 3.000s 18.594us 20 20 100.00
pwm_csr_aliasing 3.000s 139.689us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 2.567m 27.636ms 50 50 100.00
V2 pulse pwm_rand_output 2.567m 27.636ms 50 50 100.00
V2 blink pwm_rand_output 2.567m 27.636ms 50 50 100.00
V2 heartbeat pwm_rand_output 2.567m 27.636ms 50 50 100.00
V2 resolution pwm_rand_output 2.567m 27.636ms 50 50 100.00
V2 multi_channel pwm_rand_output 2.567m 27.636ms 50 50 100.00
V2 polarity pwm_rand_output 2.567m 27.636ms 50 50 100.00
V2 phase pwm_rand_output 2.567m 27.636ms 50 50 100.00
V2 lowpower pwm_rand_output 2.567m 27.636ms 50 50 100.00
V2 perf pwm_perf 53.000s 11.055ms 50 50 100.00
V2 stress_all pwm_stress_all 5.667m 56.892ms 49 50 98.00
V2 alert_test pwm_alert_test 8.000s 42.445us 50 50 100.00
V2 intr_test pwm_intr_test 3.000s 17.651us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 6.000s 106.144us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 6.000s 106.144us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 3.000s 21.195us 5 5 100.00
pwm_csr_rw 3.000s 18.594us 20 20 100.00
pwm_csr_aliasing 3.000s 139.689us 5 5 100.00
pwm_same_csr_outstanding 4.000s 137.794us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 3.000s 21.195us 5 5 100.00
pwm_csr_rw 3.000s 18.594us 20 20 100.00
pwm_csr_aliasing 3.000s 139.689us 5 5 100.00
pwm_same_csr_outstanding 4.000s 137.794us 20 20 100.00
V2 TOTAL 289 290 99.66
V2S tl_intg_err pwm_tl_intg_err 4.000s 87.828us 20 20 100.00
pwm_sec_cm 3.000s 791.402us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 4.000s 87.828us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 419 420 99.76

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.60 99.55 99.20 99.88 95.41 94.92 -- 100.00 99.01

Failure Buckets

Past Results