69c572b503| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 5.000s | 1.039ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 2.000s | 88.135us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 3.000s | 68.049us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 10.000s | 467.045us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 3.000s | 303.787us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 4.000s | 54.049us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 3.000s | 68.049us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 3.000s | 303.787us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 3.600m | 22.343ms | 49 | 50 | 98.00 |
| V2 | pulse | pwm_rand_output | 3.600m | 22.343ms | 49 | 50 | 98.00 |
| V2 | blink | pwm_rand_output | 3.600m | 22.343ms | 49 | 50 | 98.00 |
| V2 | heartbeat | pwm_rand_output | 3.600m | 22.343ms | 49 | 50 | 98.00 |
| V2 | resolution | pwm_rand_output | 3.600m | 22.343ms | 49 | 50 | 98.00 |
| V2 | multi_channel | pwm_rand_output | 3.600m | 22.343ms | 49 | 50 | 98.00 |
| V2 | polarity | pwm_rand_output | 3.600m | 22.343ms | 49 | 50 | 98.00 |
| V2 | phase | pwm_rand_output | 3.600m | 22.343ms | 49 | 50 | 98.00 |
| V2 | lowpower | pwm_rand_output | 3.600m | 22.343ms | 49 | 50 | 98.00 |
| V2 | perf | pwm_perf | 52.000s | 37.492ms | 49 | 50 | 98.00 |
| V2 | stress_all | pwm_stress_all | 5.133m | 525.056ms | 46 | 50 | 92.00 |
| V2 | alert_test | pwm_alert_test | 3.000s | 25.688us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 3.000s | 71.304us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 6.000s | 591.307us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 6.000s | 591.307us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 2.000s | 88.135us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 68.049us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 3.000s | 303.787us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 3.000s | 124.860us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 2.000s | 88.135us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 68.049us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 3.000s | 303.787us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 3.000s | 124.860us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 284 | 290 | 97.93 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 5.000s | 266.607us | 20 | 20 | 100.00 |
| pwm_sec_cm | 3.000s | 75.874us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 5.000s | 266.607us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 414 | 420 | 98.57 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 4 | 57.14 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.62 | 99.48 | 99.08 | 99.96 | 95.51 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 4 failures:
4.pwm_stress_all.27611862143540581590904420410635572197863810057961174576401557351561482195399
Line 389654, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/4.pwm_stress_all/latest/run.log
UVM_ERROR @ 66194009990 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [5] did not MATCH
UVM_INFO @ 66194009990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.pwm_stress_all.80027857738828389638662069555999076842425864827439007947000759466708187300257
Line 9513211, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/6.pwm_stress_all/latest/run.log
UVM_ERROR @ 65446502860 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [0] did not MATCH
UVM_INFO @ 65446502860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test pwm_perf has 1 failures.
47.pwm_perf.11998616860418789609422094388625078992719738690258409710660819782704411561890
Line 375, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/47.pwm_perf/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test pwm_rand_output has 1 failures.
48.pwm_rand_output.107495444362867847793797393387910488179422227059493811012477940850354828463828
Line 1617, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/48.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---