PWM Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: `00fe426038`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	5.000s	751.935us	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	35.312us	5	5	100.00
V1	csr_rw	pwm_csr_rw	3.000s	16.030us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	10.000s	1.361ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	395.318us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	3.000s	80.038us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	3.000s	16.030us	20	20	100.00
		pwm_csr_aliasing	4.000s	395.318us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.317m	43.739ms	50	50	100.00
V2	pulse	pwm_rand_output	1.317m	43.739ms	50	50	100.00
V2	blink	pwm_rand_output	1.317m	43.739ms	50	50	100.00
V2	heartbeat	pwm_rand_output	1.317m	43.739ms	50	50	100.00
V2	resolution	pwm_rand_output	1.317m	43.739ms	50	50	100.00
V2	multi_channel	pwm_rand_output	1.317m	43.739ms	50	50	100.00
V2	polarity	pwm_rand_output	1.317m	43.739ms	50	50	100.00
V2	phase	pwm_rand_output	1.317m	43.739ms	50	50	100.00
V2	lowpower	pwm_rand_output	1.317m	43.739ms	50	50	100.00
V2	perf	pwm_perf	50.000s	21.002ms	50	50	100.00
V2	stress_all	pwm_stress_all	6.233m	293.977ms	48	50	96.00
V2	alert_test	pwm_alert_test	3.000s	15.816us	50	50	100.00
V2	intr_test	pwm_intr_test	3.000s	42.480us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	6.000s	543.375us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	6.000s	543.375us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	35.312us	5	5	100.00
		pwm_csr_rw	3.000s	16.030us	20	20	100.00
		pwm_csr_aliasing	4.000s	395.318us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	122.912us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	35.312us	5	5	100.00
		pwm_csr_rw	3.000s	16.030us	20	20	100.00
		pwm_csr_aliasing	4.000s	395.318us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	122.912us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	pwm_tl_intg_err	5.000s	158.748us	20	20	100.00
		pwm_sec_cm	3.000s	265.928us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	5.000s	158.748us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			418	420	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.46	99.41	98.95	99.96	94.89	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

1.pwm_stress_all.38635182883724826437224503950877659750586712011271108153179068660142130050280
Line 1049400, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/1.pwm_stress_all/latest/run.log

  UVM_ERROR @ 47935822604 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [3] did not MATCH
  UVM_INFO @ 47935822604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.pwm_stress_all.108770540977405297832591293388806025271719944266683383157776946743840389158917
Line 553, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/34.pwm_stress_all/latest/run.log

  UVM_ERROR @ 97409582980 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [1] did not MATCH
  UVM_INFO @ 97409582980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---